Globalfoundries Inc.

Juhi Bansal

Zhi-Yuan Wu

Jia Feng

Srinath Krishnan

Kevin J Yang

Sriram Balasubramanian

Lingquan Wang

Vineet Wason

Karthik Chandrasekaran

Varsha Balakrishnan

Arunima Dasgupta

A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Modeling gate transconductance in a sub-circuit transistor model

An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

Sub-circuit models with corner instances for VLSI designs

Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Ibased on the local Monte Carlo simulations around process corner G, extrapolating the worst case Ifrom the normal probability distribution of Ito define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner. Embodiments further include creating a library of SRM corner values for multiple SRAM cells, and validating an SRAM cell by selecting an SRM corner from the library. Embodiments further include linearly scaling the SRM corner value with global sigma input variations from 0 sigma to 6 sigma and/or with local sigma input variations from 0 sigma to 6 sigma, selecting a scaled SRM corner value at the sigma corresponding to design and memory size requirements for the SRAM cell, simulating the scaled SRM corner by a processor, and employing the simulated scaled SRM corner to validate performance of an SRAM cell.

Model library implementation and methodology for worst case performance modeling for SRAM cells

Growing community of inventors

Sunnyvale, CA, United States of America

Juhi Bansal