Nokia Mobile Phones Limited

Other

Nokia Telecommunications Oy

Juha H Rapeli

Ilkka Antero Keskitalo

Juha Kostamovaara

Kari Rikkinen

Tero Ojanpera

Pentti Leppanen

Kari Kananen

Savo Glisic

Jose De Albuquerque Epifanio Da Franca

Aarne H Tenhunen

Seppo Leppavuori

Jorma J Makinen

Carlos Mexia De Almeida De Azeredo Leme

Yrjo A Neuvo

Timo Rahkonen

Ricardo Dos Santos Reis

Pedro Antonio De Sousa Cardoso Lopes

Markku K Renfors

Joao Paulo Zuna Bello

The present invention relates to a method and a simulator for simulating an RF channel between a radio transmitter and a radio receiver located at a far distance from one another, in which radio channel multipath propagation occurs, and with which simulation at least part of the phenomena caused by the multipath propagation to the radio signal, such as delay spread, attenuation and Doppler shift are implemented. As taught by the method, an RF signal (f.sub.in) is moved to a lower frequency (f.sub.IF), and from said lower frequency signal (f.sub.IF) thus produced samples are taken and written in a memory at a predetermined write frequency (f.sub.w). The stored samples are read from the memory after a period of time of the length of the propagation delay (t.sub.Di) of each propagation path (i) to be simulated from the storage in the memory at a read frequency (f.sub.Pi) predetermined for each propagation path (i) to be simulated, said read frequency differing from the write frequency (f.sub.w), when the frequency difference (.DELTA.f.sub.01) of said write frequency (f.sub.w) and the propagation-specific read frequency (f.sub.Ri) represent the Doppler shift of the frequency occurring in each propagation path (i).

RF channel simulator

Method and circuit for creating a modulated signal in a transceiver

The invention relates to a circuit arrangement for generating two signals having a phase difference of approximately 90 degrees. The invention is preferably applied in the demodulator of a radio receiver. In order to shift the phase of a signal one idea of the invention is to use a distributed resistance/capacitance circuit or a distributed RC circuit (Z.sub.10, Z.sub.20) in connection with a signal amplifying means (A.sub.1, A.sub.2). The operation of the circuit is not frequency dependent and a circuit adjustment is not necessarily required in order to calibrate the phase difference, because the distributed RC circuit can provide an substantially constant phase shift of .+-.45 degrees over a wide frequency range. The whole circuit can be integrated into one component, because a distributed RC circuit is easily made on the same integrated circuit substrate as the amplifying means, and thus the circuits can be made into a small size and at low manufacturing costs.

Circuit arrangement for generating signals with different phases

A charge transfer from signal voltage (U.sub.S) to integrating capacitance (C.sub.O) is accomplished by means of charge transfer capacitance (C.sub.i), an active element (T) and controllable switches (S.sub.61, S.sub.62, S.sub.63, S.sub.64). The operation of the circuit is additionally based on the fact that the charge transfer to the charge transfer capacitance (C.sub.i) is terminated when the transistor (T) is in a current-carrying state and that current flow is ensured by a constant-current element set. These features are combined preferably in such a way that the breaking current of charge transfer is equally great as previously said current of the constant-current element.

Two phase low energy signal processing using charge transfer capacitance

The object of the invention is a field-effect transistor comprising a drain (D) and a source (S) and a gate (G) with a determined width (W) and length (L), equipped with means (G1-G2) for generating a voltage distribution on the gate in direction of its width. The gate comprises a first end in direction of its width and a second end essentially opposite to the first end, and that a first gate contact (G1) is arranged at the first end for providing a first voltage (V.sub.G1) to the first end, and a second gate contact (G2) is arranged at the second end for providing a second voltage (V.sub.G2) to the second end, for generating a voltage distribution on the gate in direction of its width with the help of a difference voltage (V.sub.G1 -V.sub.G2) between the first (G1) and the second (G2) gate contact. On the basis of the first (V.sub.G1) and second (V.sub.G2) voltage, a determined common-mode voltage is obtained on the gate, by which the voltage level of the gate is adjusted, and the difference voltage can be used for the adjustment of the voltage distribution in the width direction of the gate. In addition, a third gate contact (G3) can be arranged on the gate for generating a determined potential (V.sub.G3) as a common voltage evenly over the entire gate area. As an output (I.sub.DS), a signal proportional to the product of the difference voltage (V.sub.G1 -V.sub.G2) and common-mode voltage is obtained from the field-effect transistor thereby forming a multiplier.

Field effect transistor utilizing the gate structure two-dimensionally

The invention relates to a transceiver for generating complex I/Q-signals on a transmission frequency (f.sub.TX) and for receiving them on a reception frequency (f.sub.RX). The device comprises a first frequency synthesizer (41) for forming a first mixer signal (f.sub.LI) for the mixer (42) of the first branch that mixes the I-component of the received signal into a lower-frequency I-signal, and a second frequency synthesizer (411, 49, 46) for forming a second mixer signal (f.sub.LQ) for the mixer (421) of the second branch that mixes the Q-component of the received signal into a lower-frequency Q-signal. The device further comprises control means (45) first for directing the phase of the first (f.sub.LI) and the second (f.sub.LQ) mixer signals into the same phase in the mixing effects thereof and, thereafter, into a 90 degree mutual phase shift in the mixing effects thereof when receiving signals for bringing the lower-frequency I- and Q-signals into a 90 degree mutual phase shift.

Transceiver and method for generating and processing complex I/Q-signals

Data transmission method, base station, and subscriber terminal

A frequency difference signal of a modulated signal (f.sub.1) and an unmodulated signal (f.sub.2) is produced maintaining the information of the frequency or phase modulation. According to the method, the time-related order of entry of the front edges of the pulses of the modulated and the unmodulated signal is controlled and the edge of the frequency difference signal in question at any moment is formed timewise at the same point as the edge of such modulated signal at which the time-related order of arrival of the modulating signal and the unmodulated signal has changed. Hereby, the frequency or phase shift of the modulated signal can be detected as an equivalent change in the frequency difference signal, and the modulation of the frequency difference signal is detected on the basis of the location of the pulse edge of the frequency difference signal.

Method and apparatus for producing a difference signal between two

The present invention relats to a method for processing a signal, and a signal processing circuit according to the method, in which circuit one or two transistors (T1, T2) switched according to the switches are used as the active member of the entire circuit, the charge passing through said transistors being controlled, in addition to the switches, by the transferrable charge itself so that on concluded transfer of charge, all current flow in the circuit stops by itself. By means of the present invention, the signal processing is, irrespective of the polarity of the signal (positive or negative) and of the threshold voltages (Uth1, Uth2) of the transistors, linear because the signal voltage (U.sub.s) is produced, as taught by the invention, relative to a reference voltage (U.sub.Ref) of predetermined magnitude in that a sum of the signal voltage (U.sub.s) and said reference voltage (U.sub.Ref) is produced and the polarity of said sum is every time the same as the polarity of the reference voltage (U.sub.Ref), irrespective of the variation of the signal voltage (U.sub.s), and when charge samples proportional to the signal voltage (U.sub.s) are taken, a quantity thereof is taken which is proportional to the sum (U.sub.s + U.sub.Ref) of the signal voltage (U.sub.s) and the reference voltage (U.sub.Ref), whereby the charge samples pro-portional to said sum (U.sub.s + U.sub.Ref) are transferred to the integrating capacitance (C.sub.o) included in the circuit, and thereafter, a quantity of charge samples proportional to the reference voltage (U.sub.Ref) is added into the integrating capacitance (C.sub.o) with an opposite polarity relative to the polarity of the charge samples proportional to said sum (U.sub.s + U.sub.Ref).

Method and apparatus for processing signals

An integrating circuit is formed in the present invention, of which the active element is a pair of bipolar transistors (T5/T6) or a CMOS transistor (T8) which with the aid of switches (s81 to s88) controls the storing of a sample charge from the signal voltage (Us) in a sampling capacitor (Ci) and the discharging of the sample into an integrating capacitor (Co). The circuit only consumes current while charges are being transferred.

Method and circuit for dynamic voltage intergration

The invention relates to a method, in which a phase modulated or frequency modulated signal can be directly generated with a PLL frequency synthesizer. With an interpolating synthesizer it is possible to create a very dense output frequency (f.sub.x) raster, so that the pulses received in the phase comparator (63) both from the reference signal (f.sub.o) branch and from the voltage controlled oscillator VCO (65) are lengthened in lengthening means (62, 69; 67, 68; k.sub.1, L+.DELTA.L; k.sub.2, L) by a desired amount. The numbers k.sub.1 and k.sub.2 are proportional to the amount of lengthening. When these integers now further are changed proportionally to the modulating signal, the change of the integers causes a change of the time difference of the pulses received by the phase comparator (63). This change of the time difference further causes a change in the output signal (f.sub.x) of the voltage controlled oscillator. The method is particularly well suited to provide digital quadrature phase modulation QPSK or quadrature amplitude modulation QAM, in which the shift from one carrier phase to another has a predetermined size and waveform as a function of time.

Method and circuit arrangement to generate a phase modulated or

The present invention relates to a method for eliminating noise in a signal. The frequency band of the signal is divided into sub-bands, whereafter the useful value of the signal of each sub-band is determined by comparing the signal level to a reference level, in which case a constant signal of substantially the same level as the reference level is suppressed as noise and a varying signal, defined as a useful signal, is combined, unsuppressed, with the useful signals of the other sub-bands. The frequency band of the channel is divided into sub-bands by means of an all-pass filter construction. The method can be implemented using an analog or a digital filter construction.

Noise elimination method

An FM or PM signal is demodulated so that the cycle time of the modulated input signal is measured using a time-to-digital converter comprising a counter that uses a moderate clock frequency as a reference clock, a digital delay line interpolator and a control circuitry. The counter is used for rough digitization and the delay line for interpolating the moment of zero-crossing inside a clock cycle. Total delay of the delay line, i.e., the range of time intervals the interpolator is able to measure, is actively kept equal to the cycle time of the reference clock. When the number of delay elements in the delay line is a power of two, the result of the delay line interpolator may be used directly as the least significant bits of the measurement.

Method and circuitry for demodulation of angle modulated signals by

The invention concerns are interpolating frequency synthesizer based on digital phase locking, with which frequencies can be produced which lie between frequencies defined by integer divisors. Traditional frequency synthesizers employ frequency dividers in which the dividing ratio is an integer. The circuit of the invention comprises member (8, 9), in one of which the reference frequency (f.sub.o) or the VCO frequency (f.sub.x), or the frequency obtained from them by division, is multiplied with a coefficient L and in the other member the corresponding frequency is multiplied by L+ .DELTA.L; and members (2, 7), in which the first pulses going to the phase detector (3) are lengthened by a time corresponding to a given integer number k1 of pulses formed in the number (8), and the other pulses are lengthened by a time corresponding to a given integer number k2 of pulses formed in the member (9).

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Oulu, Finland

Juha H Rapeli