Friedrich-alexander-universitaet Erlangen-nuernberg

Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

Juergen Teich

Dirk Koch

Thilo Streichert

Christian Haubelt

Daniel Ziener

A logic chip has a plurality of individually-addressable resource blocks, each comprising logic circuitry. The logic chip also has a bus comprising a plurality of bus information lines. A first of the resource blocks has a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block. A second of the resource blocks, which is adjacent to the first resource block, has a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks. The first and second sub-sets have different bus lines.

Logic chip, method and computer program for providing a configuration information for a configurable logic chip

A watermarking apparatus for an electronic circuit is described, which comprises the following features: a watermark memory operative to store a watermark characterizing said electronic circuit, and a watermarking signal generator operative to generate based on said watermark a watermarking signal on a power supply line of said electronic circuit, wherein said watermarking signal is detectable for a recognition of said watermark.

Watermarking apparatus, software enabling an implementation of an electronic circuit comprising a watermark, method for detecting a watermark and apparatus for detecting a watermark

A logic chip has a plurality of individually addressable resource blocks each of the resource blocks having logic circuitry, and a communication bar extending across a plurality of the individually addressable resource blocks. The communication bar has a plurality of communication bar segments associated with the resource slots. The communication bar segments of the individually addressable resource blocks have identical interface locations with respect to boundaries of the resource blocks, such that an input interface location of a first resource block matches an output interface location of an adjacent second resource block. At least one of the individually addressable resource blocks has a bypass segment of the communication bar. At least one of the individually addressable resource blocks has an access segment of the communication bar. The access segment has an access structure inserted between a first communication bar interface location and a second communication bar interface location, to allow for a read access or a write access or a combined read/write access to the communication bar.

Growing community of inventors

Erlangen, Germany

Juergen Teich