Other

Juergen T Rickes

Hugh Pryor McAdams

James W Grace

John Y Fong

Ralph H Lanham

Scott Robert Summerfelt

Sudhir Kumar Madan

Yacoub Mustafa

Ralph H R Lanham

A FeRAM includes a reference voltage calibration circuit that evaluates FeRAM cells and selects reference voltages for reading the FeRAM cells. Calibration of the reference voltage can be performed dynamically during normal operation of the FeRAM so that the reference voltage tracks changes in FeRAM cell performance that may be associated with temperature or aging effects. Dynamic calibration during normal use eliminates the need for a reference voltage calibration process during manufacture of the memory. The calibration circuit can further be connected to redundancy circuitry that replaces FeRAM cells that the calibration circuit determines are weak.

Dynamic reference voltage calibration integrated FeRAMS

A method and circuit for determining the accuracy of a measurement of a bit line voltage or a charge distribution for readout from FeRAM cells uses sense amplifiers to compare a bit line voltage to a series of reference voltages and then determines upper and lower limits of a range of range of reference voltages for which sensing operation provide inconsistent results. One embodiment uses an output signal of a sense amplifier to control a pull-down transistor of an I/O line and alternative precharging schemes for the I/O line allow determining both limits using the same compression circuitry to process a result value stream on the I/O line.

Accuracy determination in bit line voltage measurements

Methods and apparatus are disclosed for selectively coupling sense amps with local IO lines in memory devices, comprising first and second selection systems operable to selectively couple a sense amp terminal with a local IO line. A first selection system is coupled with a local IO line and a sense amp, providing selective coupling thereof a second time period after the sense amp is enabled. A second selection system is coupled with the local IO line and the sense amp, which couples the local IO line with the sense amp a first time period before the sense amp is enabled during a write operation, wherein the first time period may be zero.

Sense amplifier with override write circuitry

A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Accelerated fatigue testing

A method and circuit for measuring a charge distribution for readout from a memory such as a FeRAM uses on-chip compression of bit line voltage measurements. One embodiment includes a compression circuit coupled to sense amplifiers. Each sense amplifier compares a series of reference voltages to a corresponding bit line and sets a result value for the comparison. A series of result values from a sense amplifier has a transition when the bit line voltage is approximately equal to the reference voltage. The compression circuit can use the transition as a trigger to record a compressed value indicating the reference voltage at the transition.

On-chip compression of charge distribution data

A comparator-type sense amplifier compares a constant voltage that was read out of a FeRAM cell to a sequence of reference voltage levels. A multiple-comparison operation includes (a) reading out data to a bit line, (b) applying a first/next reference voltage, (c) comparing the bit line voltage to the applied reference voltage, and (d) repeating steps (b) and (c) one or more times. The multiple comparison operation can be used to characterize operation of an FeRAM cell, predict or detect an FeRAM cell that may introduce a bit error, or to read a multi-bit value from an FeRAM cell.

FeRAM with a single access/multiple-comparison operation

An integrated circuit device includes a two-dimensional array of ferroelectric memory cells in which plate lines within the array are grouped. The grouping of plate lines accommodates the use of larger plate line drivers, such as CMOS driver inverters. Each plate line group may include some but not all of the rows of memory cells and some but not all of the columns of memory cells within the array.

Grouped plate line drive architecture and method

A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.

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Cupertino, CA, United States of America

Juergen T Rickes