Infineon Technologies Ag

Infineon Technologies Austria Ag

Juergen Steinbrenner

Ravi Keshav Joshi

Markus Kahn

Gerhard Schmidt

Matthias Kuenle

Oliver Humbel

Martin Poelzl

Roman Roth

Christian Maier

Helmut Schoenherr

Harald Huetter

Kurt Pekoll

Hans-Joachim Schulze

Romain Esteve

Johannes Baumgartl

Frank Hille

Holger Schulze

Carsten Schaeffer

Georg Ehrentraut

Frank Umbach

Thomas Laska

Angelika Koprowski

Martin Sporn

Petra Fischer

Gerald Unegg

Soenke Pirk

Andreas Haghofer

Michael Fugger

Christoph Gruber

Philipp Sebastian Koch

Rudolf Kogler

Wolfgang Dastel

Anna-Katharina Kaiser

Julia-Magdalena Straeussnigg

Oliver Blank

Dethard Peters

Werner Schustereder

Jens Peter Konrath

Christian Fachmann

Andreas Riegler

Uwe Hoeckele

Wolfgang Jantscher

Bernd Zippelius

Jochen Hilsenbeck

Herbert Gietler

Heimo Hofer

Kurt Matoy

Manfred Pippan

Hubert Maier

Andreas Behrendt

Christian Stahlhut

Alexander Binter

Christian Krenn

Waqas Mumtaz Syed

Johann Schmid

Richard Gaisberger

Johanna Schlaminger

Matthias Müller

Matthias Mueller

Philipp Koch

Elfriede Kraxner Wellenzohn

Silvana Fister

Christoph Brunner

Paul Salmen

Tobias Schmidutz

Vice Sodan

Anita Satz

Mario Stanovnik

A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.

Semiconductor device with first and second portions that include silicon and nitrogen

Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

Passivation structuring and plating for semiconductor devices

According to various embodiments, a wafer chuck may include at least one support region configured to support a wafer in a receiving area; a central cavity surrounded by the at least one support region configured to support the wafer only along an outer perimeter; and a boundary structure surrounding the receiving area configured to retain the wafer in the receiving area.

Wafer chuck and processing arrangement

A semiconductor device comprises a structured metal layer. The structured metal layer lies above a semiconductor substrate. In addition, a thickness of the structured metal layer is more than 100 nm. Furthermore, the semiconductor device comprises a covering layer. The covering layer lies adjacent to at least one part of a front side of the structured metal layer and adjacent to a side wall of the structured metal layer. In addition, the covering layer comprises amorphous silicon carbide.

Semiconductor device, microphone and methods for forming a semiconductor device

An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.

Semiconductor device including a passivation structure and manufacturing method

A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

Semiconductor device with a portion including silicon and nitrogen and method of manufacturing

In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.

Nanotube structure based metal damascene process

According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

Silicon carbide semiconductor device having a metal adhesion and barrier structure and a method of forming such a semiconductor device

According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

Semiconductor device having a metal adhesion and barrier structure and a method of forming such a semiconductor device

Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.

Forming recombination centers in a semiconductor device

According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

Semiconductor wafer and method for processing a semiconductor wafer

A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

Self aligned silicon carbide contact formation using protective layer

In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes.

Growing community of inventors

Noetsch, Austria

Juergen Steinbrenner