International Business Machines Corporation

Juergen Pille

Dieter F Wendel

Rolf Sautter

Tobias Werner

Michael B Kugel

Sebastian Ehrenreich

Alexander Fritsch

Yuen H Chan

Albert Frisch

Jens Leenstra

Philipp Salz

Thomas Kalla

Wolfgang Gellerich

Peter Altevogt

Otto M Wagner

Wolfgang Penth

Martin Bernhard Schmidt

Stefan Buettner

Chad Allen Adams

Martin Eckert

Otto Andreas Torreiter

Stefan Payer

Ulrich Krauch

Jens Noack

Antje Mueller

Christian Schweizer

Derick Gardner Behrends

Juergen Koehl

Helmut Schettler

Guenter Mayer

Shankar Kalyanasundaram

Osama Dengler

Karl-Eugen Kroell

Rajiv V Joshi

Sang Hoo Dhong

Christoph Raisch

William Vincent Huott

George McNeil Lattimore

Anthony Gus Aipperspach

Harry S Barowski

Osamu Takahashi

Uwe Brandt

Michael Ju Hyeok Lee

Michael J Lee

Robert R Livolsi

Alexander Albert Woerner

Werner Juchmes

Matthias Pflanz

Klaus Helwig

Klaus Thumm

Scott Raymond Cottier

Thomas Froehnel

Torsten Mahuke

Oto Wagner

The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.

Erasing a partition of an SRAM array with hardware support

An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.

Integrated circuit including logic circuitry

The disclosure relates to an initialization circuit for initializing memory cells of a memory array. The individual memory cells are coupled to a common bit line of the memory array via at least one pass element of the individual memory cells. Each individual memory cell comprises a charge-based storage element including a capacitance. The initialization circuit activates the pass elements of a plurality of the memory cells to be initialized such that the capacitances of the plurality of memory cells are connected simultaneously to the common bit line. Further, aspects of the disclosure relate to a method for initializing memory cells and a semiconductor circuit.

Semiconductor circuit including an initialization circuit for initializing memory cells and clearing of relatively large blocks of memory

Various aspects of the present invention disclose a test device that includes a retaining element retaining one or more nuclear radiation sources for performing a nuclear radiation stress test of data storage structures of integrated circuits on a wafer in a wafer prober. The retaining element includes one or more apertures for applying nuclear radiation from the one or more nuclear radiation sources to the data storage structures. The retaining element is configured for controlling the nuclear radiation applied via the one or more apertures. The controlling includes a varying of relative positions of the one or more nuclear radiation sources and the one or more apertures. Additional aspects of the present invention disclose a testing method, computer program product, and computer system for performing the nuclear radiation stress test. In an example aspect, embodiments of the present invention disclose a test device for a wafer prober.

Stressing integrated circuits using a radiation source

An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.

Integrated circuit with vertical structures on nodes of a grid

An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.

Microelectronic device with a memory element utilizing stacked vertical devices

Embodiments of memory block erasure are described herein. An aspect includes determining an initial word line set consisting of a single word line. Another aspect includes activating the single word line such that a first memory cell that is connected to the single word line is erased by the activation. Another aspect includes determining a first word line set consisting of the single word line and one additional word line, and wherein the one additional word line corresponds to a second memory cell have a maximum distance from the first memory cell along a bit line that includes the first memory cell and the second memory cell. Another aspect includes activating the first word line set, such that a respective memory cell that is connected to each of the first word line set is erased by the activation.

Memory block erasure

An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.

Buried conductive layer supplying digital circuits

An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.

Microelectronic device utilizing stacked vertical devices

Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.

Build synthesized soft arrays

Embodiments of memory block erasure are described herein. An aspect includes determining a first word line set consisting of a first plurality of word lines. Another aspect includes activating the first plurality of word lines, such that a respective memory cell that is connected to each of the first plurality of word lines is erased by the activation of the first plurality of word lines. Another aspect includes determining a second word line set, wherein the second word line set consists of the first word line set and a second plurality of word lines. Another aspect includes simultaneously activating the first plurality of word lines and the second plurality of word lines, such that a respective memory cell that is connected to each of the second plurality of word lines is erased by the activation of the first plurality of word lines and the second plurality of word lines.

A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.

Current-mode sense amplifier

In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.

Activation of memory core circuits in an integrated circuit

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Stuttgart, Germany

Juergen Pille