Infineon Technologies Ag

Infineon Technologies LLC

Juergen Lindolf

Till Schloesser

Valentin Rosskopf

Andreas Felber

Bernhard Kowalski

Thoai-Thai Le

Bernd Goebel

Bernd Klehn

Guenter Gerstmeier

An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines. The test structure provides a convenient means to carry out reliability investigations on the gate oxide of the vertical FET transistors and on the capacitor dielectric in the deep trenches, capacitance measurements between the word lines, and between the word lines and other circuit layers, as well as capacitance measurements between the bit lines and between the bit lines and other circuit layers, and thus facilitates diagnosis of possible fault sources arising during the production process.

Device architecture and process for improved vertical memory arrays

An integrated circuit arrangement that has an integrated test structure is provided. The integrated circuit arrangement includes a transistor array having vertical FET selection transistors electrically coupled to storage capacitors of an assigned memory cell array, the storage capacitors being formed vertically into the depth of a substrate in deep trenches. The test structure may enable a plurality of vertical FET selection transistors by a conductive electrode material embedded in an extended deep trench. With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.

Test structure for improved vertical memory arrays

A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.

Auto-adjustment of self-refresh frequency

A measurement probe for detecting electrical signals in an integrated circuit on a semiconductor chip has a lever arm and a probe tip which is configured on the lever arm. The lever arm is made of a highly conductive material that is covered by an extremely thin insulator layer. The probe tip has a window in the insulator layer at the apex point, and the lever arm makes contact through the insulator layer. This measurement probe can be operated in a force mode and in a tunneling mode, in order to move to a measurement point on the integrated circuit with high positioning accuracy, and to detect the electrical signals at this measurement point.

Growing community of inventors

Friedberg, Germany

Juergen Lindolf