Infineon Technologies Ag

Hyundai Motor Company

Infineon Technologies Austria Ag

Bundesdruckerei Gmbh

Kia Motor Corporation

Juergen Hoegerl

Gottfried Beer

Olaf Hohlfeld

Andreas Grassmann

Frank Pueschner

Volker Strutz

Ivan Nikitin

Thomas Killer

Gerold Gruendler

Edward Fuergut

Wolfram Hable

Erich Syri

Peter Stampka

Ordwin Haase

Magdalena Hoier

Tobias Kist

Georg Meyer-Berg

Angela Kessler

Peter Kanschat

Peter Scherl

Christian Schweikert

Achim Strass

Horst Theuss

Martin Gruber

Rainer Markus Schaller

Leo Aichriedler

Irmgard Escher-Poeppel

Alexander Roth

Andre Arens

Gerald Wriessnegger

Wolfgang Schindler

Andreas Mueller-Hipper

Hans-Joachim Schulze

Jens G Pohl

Klaus Elian

Guenther Ruhl

Jochen Dangelmaier

Hans-Joerg Timme

Thilo Stolze

Mathias Vaupel

Joerg Fischer

Manfred Fries

Stephan Bradl

Peter Ossimitz

Thomas Mueller

Michael Huber

Raimund Foerg

Holger Torwesten

Horst Groeninger

Stephan Rampetzreiter

Markus Tietke

Robert Allinger

Martin Buchsbaum

Ottmar Geitner

Michael Ledutke

Bernd Betz

Waldemar Jakobi

Andreas Munding

Frank Winter

Andreas Karl

Tao Hong

Eduard Knauer

Tino Karczewski

Roman Hollweck

Hermann Josef Lutz

Erick Syri

Thomas Pfaffelhuber

Matthias Lassmann

Daniel Obermeier

Kiyoung Jang

Stefan Troelenberg

Kristof Bothe

Uwe Wagner

A semiconductor module includes a semiconductor die, a mold compound encasing the semiconductor die, a plurality of terminals electrically connected to the semiconductor die and protruding out of the mold compound, wherein a first one of the terminals has a constricted region covered by the mold compound, wherein the mold compound has a recess or an opening near the constricted region of the first terminal, and a coreless magnetic field sensor disposed in the recess or the opening of the mold compound and isolated from the first terminal by the mold compound. The coreless magnetic sensor is configured to generate a signal in response to a magnetic field produced by current flowing in the constricted region of the first terminal. The magnitude of the signal is proportional to the amount of current flowing in the constricted region of the first terminal. A method of manufacturing the module also is described.

Semiconductor module with external power sensor

A semiconductor package includes an encapsulant body; a first electrically conductive element having an outwardly exposed metal surface; a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the first electrically conductive element and the first electrically conductive layer; a power semiconductor chip between the first electrically conductive element and the first electrically conductive layer; and a second electrically conductive spacer between the first electrically conductive element and the power semiconductor chip, a first carrier region of the first electrically conductive layer is connected to a first power terminal, a second carrier region of the first electrically conductive layer is alongside the first carrier region and is connected to a second power terminal, a first region of the first electrically conductive element is connected to a third power terminal.

Double-sided coolable semiconductor package

A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

Fluid-cooled package having shielding layer

A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.

Power semiconductor module and method for fabricating the same

A semiconductor package includes an encapsulant body; an upper electrically conductive element having an outwardly exposed metal surface; a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the upper electrically conductive element and the upper electrically conductive layer; a power semiconductor chip between the upper electrically conductive element and the upper electrically conductive layer; and a second electrically conductive spacer between the upper electrically conductive element and the power semiconductor chip, a first carrier region of the upper electrically conductive layer is connected to a first power terminal, a second carrier region of the upper electrically conductive layer is alongside the first carrier region and is connected to a phase terminal, a first region of the upper electrically conductive element is connected to a second power terminal.

Double sided semiconductor package

A sensor device comprises a dielectric substrate, a busbar mechanically connected to the dielectric substrate, a cavity formed in the dielectric substrate, and a sensor chip arranged in the cavity, wherein the sensor chip is designed to detect a magnetic field induced by an electric current flowing through the busbar, wherein in an orthogonal projection of the sensor chip onto the busbar, the sensor chip at least partly overlaps the busbar.

Sensor devices with sensor chip and busbar

A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.

Semiconductor package and method for fabricating a semiconductor package

A sensor device comprises a busbar, a dielectric arranged on the busbar, and a sensor chip arranged on the dielectric, wherein the sensor chip is designed to measure a magnetic field induced by an electric current flowing through the busbar, wherein the surface of the dielectric facing toward the busbar is spaced from the busbar in an area along the entire periphery of the dielectric.

Sensor devices having a sensor chip and busbar

A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module

A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.

Package cooled with cooling fluid and comprising shielding layer

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer with an outwardly exposed surface and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a passive electrical component electrically connected to the upper electrically conductive layer of the lower carrier substrate.

Semiconductor package with passive electrical component and method for the production thereof

A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase. A first region of the upper electrically conductive element is configured to apply a negative supply voltage, and at least partly overlaps the first carrier region.

Semiconductor package having overlapping electrically conductive regions and method for producing the same

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.

Semiconductor package having symmetrically arranged power terminals and method for producing the same

A semiconductor package having a double-sided cooling structure includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a shielding structure configured to electromagnetically shield a line of the semiconductor package.

Semiconductor package having an electromagnetic shielding structure and method for producing the same

A semiconductor module is disclosed. In one example, the module includes a carrier, at least one semiconductor transistor disposed on the carrier, at least one semiconductor diode disposed on the carrier, at least one semiconductor driver chip disposed on the carrier, a plurality of external connectors, and an encapsulation layer covering the carrier, the semiconductor transistor, the semiconductor diode, and the semiconductor driver chip. The semiconductor transistor, the semiconductor diode, and the semiconductor driver chip are arranged laterally side by side on the carrier.

Semiconductor module comprising transistor chips, diode chips and driver chips arranged in a common plane

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Wuppertal, Germany

Juergen Hoegerl