Motorola Corporation

Freescale Semiconductor,inc.

Juergen A Foerstner

Bor-Yuan C Hwang

Wen-Ling M Huang

Marco Racanelli

John E Schmiesing

Henry G Hughes

Melvy Freeland Miller, Iii

Myriam Combes

Guang X Li

Frank A Shemansky, Jr

Muh-Ling Ger

Paul L Bergstrom

Guy Hautekiet

Arlette Marty-Blavier

Bertrand Francis Cambou

Raymond Mervin Roop

Steven M Smith

Frank S d'Aragona

H Ming Liaw

Heemyong Park

Paul M Ocansey

Amir Raza Mirza

An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.

Integrated matching networks and RF devices that include an integrated matching network

An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming () a first die on a substrate, forming () a second die on the substrate, and forming () a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (), a second die having a capacitor (), and a metal interconnect () coupled to the PA and the first capacitor. The metal interconnect () has an inductance. The capacitor () and metal interconnect () form a shunt impedance.

Integrated matching network and method for manufacturing integrated matching networks

Methods and apparatus are provided for preparing sensing fingers for use in a highly integrated accelerometer. The method includes steps for forming a tungsten/tungsten silicide coating on a silicon finger. The tungsten/tungsten silicide coating adds mass to the silicon finger. The method includes steps of forming silicon fingers from layers of silicon, oxides, and capping material. The silicon fingers are then exposed to tungsten containing gases under conditions to promote the formation of a tungsten silicide seed layer on the exposed silicon surfaces. The tungsten layer is then grown to a desired thickness through a growth step. The coated silicon fingers display improved resistance to stiction as compared to uncoated silicon fingers.

Tungsten coated silicon fingers

A method is provided for making a MEMS structure ( ). In accordance with the method, a CMOS substrate ( ) is provided which has interconnect metal ( ) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.

Low temperature plasma Si or SiGe for MEMS applications

A sensor has an electrode (,) that is movable along three mutually perpendicular axes (,). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (,) along the three axes (,).

Sensor and method of use

A sensor has an electrode (120) that is movable along three mutually perpendicular axes (10, 11, 12). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (120) along the three axes (10, 11, 12).

A process for forming a sensor (10) such as an accelerometer includes the steps of forming an epitaxial layer (14) on a semiconductor substrate (12), patterning a portion of the epitaxial layer to provide a monocrystalline finger (20,22), wherein the finger has a height (43) at least twice its width (44), and forming a cavity (40) under at least a portion of the finger to expose a bottom surface (38) of the finger using an etchant with an etch selectivity for the semiconductor substrate relative to the epitaxial layer of greater than about 10:1. The distance (42) from the bottom of the cavity to the bottom surface of the member is greater than about 5 microns. The accelerometer is useful for lateral acceleration sensing and is built in bulk silicon at the surface of the substrate.

Semiconductor structure having a monocrystalline member overlying a

A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).

Method for fabricating a semiconductor on insulator device

A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).

Method of forming an isolation oxide for silicon-on-insulator technology

A two stage threshold adjust implantation process is performed after field oxidation to avoid the effects of dopant redistribution and segregation. At any of several steps in a manufacturing process, only routine implant energy and dose adjustments are required to create a first and a second dopant profile (110, 120) that result in the reduction of edge leakage and threshold voltage sensitivity to device layer thickness of a semiconductor device on a semiconductor on insulator substrate.

Fabrication method for a semiconductor device on a semiconductor on

A method of manufacturing an integrated circuit having a buried layer of a low doped type of conductivity (2) and a buried layer of a highly doped type of the same conductivity (3) by masking a substrate (1) so as to define open areas on the substrate where it is desired to provide the two buried layers and doping the open areas of the substrate with a low concentration of dopants to form the low doped type of buried layer (2) is formed. Then one open area where the low doped type of buried layer (2) is formed is masked and the other open area is doped with a high concentration of dopants to form the highly doped type of buried layer (3).

Method of making BiCMOS circuit

A method of manufacturing both bipolar and CMOS devices including vertical PNP, NPN, PMOS and NMOS devices on the same chip, includes the steps of, simultaneously forming an N+ region (14) on part of a P base region (11) of the vertical NPN device to form the emitter contact region thereof, an N+ region (14) on a part of an N- epitaxial layer (5) of the vertical NPN device to form the collector contact region thereof, N+ regions (14) on first and second parts of a P well region (8) of the NMOS device to form the source and drain thereof, and an N+ region (14) on an N base region (9) of the vertical PNP device to form the base contact thereof. In a further simultaneous step, there are formed P+ regions (15) on the P-well (8) and N base (9) regions of the vertical PNP device to form the collector and emitter contact regions thereof, P+ regions (15) on first and second parts of the N- epitaxial layer (5) of the PMOS device to form the source and drain thereof, and a P+ region (15) on part of the P base region (11) of the vertical NPN device to form the base contact region thereof.

Method of manufacturing BICMOS integrated circuits

A method of adjusting a threshold voltage for a semiconductor device on a semiconductor on insulator substrate includes performing a threshold voltage adjustment implant (25) after formation of a gate structure (16) to reduce the diffusion of implanted dopant (26). Reducing dopant diffusion eliminates the narrow channel effect which degrades device performance. Implanting the dopant (26) after formation of the gate structure (16) simplifies processing of semiconductor device (28) by eliminating a photolithography step which is accomplished by utilizing photoresist (21) used for a source and drain implant (22).

Method of adjusting a threshold voltage for a semiconductor device

An SOI wafer (10) is separated into a bipolar junction transistor area (18) and an MOS transistor area (19). A bipolar junction transistor having a collector region (25), and emitter region (44), an inactive base region (33), and an active base region (43) is formed on a thin film of semiconductor material (13) in the bipolar junction transistor area (18). A link between the inactive base region (33) and the active base region (43) is formed from a polysilicon spacer (42) along an edge or sidewall of emitter openings (39 or 40). Simultaneously with the formation of the bipolar junction transistor, MOS transistors are formed in the MOS transistor area (19). Electrically conductive contacts (56) in the bipolar junction transistor area (18) and the MOS transistor area (19) are formed from a silicide. Both complementary bipolar junction transistors and MOS transistors may be formed.

Method for fabricating bipolar junction and MOS transistors on SOI

A method of fabricating a silicon film with improved thickness control and low defect density. The method comprises implanting a silicon wafer (19) with hydrogen ions to produce a layer of n-type silicon (18) having a precisely controlled thickness. Bonding the n-type silicon layer (18) to an oxidized surface (17) of a handle wafer (21) while using a temperature of 200 degrees Celsius. Etching the silicon wafer (19) to the boundary of the n-type layer (18). Annealing the silicon to drive out the hydrogen ions, leaving a silicon film (18) with a precisely controlled thickness and of the same type as the original silicon wafer (19).

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Mesa, AZ, United States of America

Juergen A Foerstner