Samsung Electronics Co., Ltd.

Nanyang Technological University

Jueon Kim

Junghwan Choi

Myoungbo Kwak

Jaewoo Park

Taehyoung Kim

Seungjin Park

Jihwan Hyun

Sangyong Lee

Jihyung Ha

Youngdon Choi

Kwangyoun Kim

Kyungah Chang

Kwangryul Kim

Ikjin Jo

Dongmin Ko

Donghyun Yoon

An analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) configured to receive an input signal and a first clock signal from an external source and to output a second clock signal and a digital output signal, a decision counter configured to increment a decision count value each time when the second clock signal received from the analog-to-digital converter is applied to the decision counter, a voltage control logic configured to output a control signal based on a result of comparing the decision count value with a reference count value, and a regulator configured to output an operation voltage, wherein the ADC is configured to adjust the cycle of the second clock signal, and the voltage control logic is configured to control the regulator to output a corrected operating voltage via the control signal.

Analog-to-digital conversion circuit and operating method of the same

A home appliance includes: a camera arranged in the interior space; and at least one processor, wherein the at least one processor is configured to: obtain, through the camera, a first image including a tray that is inserted into the interior space; identify, by using the first image, a height at which the tray is inserted in the interior space; determine, according to the height at which the tray is inserted, a setting value related to capturing of an image of the interior space; and obtain, based on the determined setting value, a second image including contents placed on the tray.

Home appliance having interior space for accommodating tray at various heights and method of obtaining image by home appliance

A water level detection device capable of preventing water from overflowing due to a bumping phenomenon or excessive number of cooking objects and capable of detecting a water level inside a cookware, comprises: a first probe; a second probe; a lean angle sensor configured to detect a lean angle of the first probe and the second probe; a capacitance sensor configured to detect capacitance between the first probe and the second probe; and a processor configured to calculate a danger level of the cookware based on an intensity of a current flowing from the first probe to the second probe and the lean angle of the first probe and the second probe; and configured to determine whether the water level inside the cookware reaches the danger level based on the capacitance between the first probe and the second probe.

Water level detection device and method for controlling water level detection device

A receiver includes a voltage-to-time converter configured to sequentially output a first converted signal and a second converted signal based on a first signal, a second signal, and a time difference; a first time comparator configured to determine a first bit value based on a first first-arrival signal (FAS) and output first data including the first bit value; a delay time generator configured to select a non-target signal and a target signal based on the first bit value and from among the first converted signal and the second converted signal; and a second time comparator configured to determine a second bit value based on a second FAS and output second data including the second bit value.

Receiver, operation method thereof, and memory device

A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.

Transmitter for ultra-high speed and storage device including the same

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

Offset detector circuit for differential signal generator, receiver, and method of compensating for offset of differential signal generator

A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

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Seoul, South Korea

Jueon Kim