Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Tsinghua University

Juei-Nai Kwo

Ming-Hwei Hong

Hsien-Wen Wan

Bo-Yu Yang

Yi-Ting Cheng

Yu-Jie Hong

Yen-Hsun Lin

Keng-Yung Lin

Minghwei Hong

Tun-Wen Pi

Jen-Inn Chyi

Wei Lee

Jui-Lin Chu

Kuanhsiung Chen

Yan Dar Wu

Kun Yu Lee

Yi Jiun Lee

Chien-Hua Fu

Hsiang Pi Chang

A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

A semiconductor device includes a semiconductive channel region, a semiconductive protection layer, a gate structure, and a pair of gate spacers. The semiconductive protection layer is on and in contact with the channel. The gate structure is above the semiconductive protection layer and includes gate dielectric layer and a gate electrode. The gate dielectric layer is above the semiconductive protection layer. The gate electrode is above the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The semiconductive protection layer extends from an inner sidewall of a first one of the pair of gate spacers to an inner sidewall of a second one of the pair of gate spacers.

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, forming a high-&#x3ba; dielectric layer directly on the semiconductor layer as formed, and annealing the semiconductor layer, the high-dielectric layer, and the substrate. The semiconductor layer is a Group III-V compound semiconductor.

Semiconductor device having high-&#x3ba; dielectric layer and method for manufacturing the same

A semiconductor device includes a semiconductor substrate, a gate structure, and source/drain regions. The gate structure comprises an yttrium oxide layer over the semiconductor substrate, an aluminum oxide layer over the yttrium oxide layer, and a gate electrode on the aluminum oxide layer. The source/drain regions are on the semiconductor substrate and on opposite sides of the gate structure.

A method for manufacturing a semiconductor device includes forming a first high-k dielectric layer on a semiconductor substrate; forming a second high-k dielectric layer on the first high-k dielectric layer, in which the second high-k dielectric layer includes a material different from a material of the first high-k dielectric layer; annealing the first and second high-k dielectric layers, such that the first and second high-k dielectric layers are inter-diffused; and forming a gate electrode over the second high-k dielectric layer.

Disclosed is a wafer comprising a first layer of GaSb grown on a GaSb substrate by molecular beam epitaxy (MBE), an oxide layer deposited on the surface of the first layer, and a cap layer deposited on the surface of the oxide layer. The wafer was capped with an arsenic (As) layer after the growth of the first layer. The As layer was removed from the wafer before the oxide layer was deposited on the surface of the first layer. Also disclosed is a method of forming a wafer. The method comprises growing a first layer of GaSb on a GaSb substrate by MBE, capping the wafer with an As layer after the growth of the first layer, removing the As layer from the wafer, depositing an oxide layer on the surface of the first layer, and depositing a cap layer on the surface of the oxide layer.

Using molecular beam epitaxy in a semiconductor structure with a high K/GaSb interface

The present invention provides a method for forming substrates for MOS (metal oxide semiconductor) transistor, comprising the following steps: (A) In a reduced-pressure environment having a pressure lower than 1&#xd7;10Torr, a base for accomplishing the surface reconstruction and a solid-state metal oxide source is provided, wherein the solid-state metal oxide source is chosen from the group consisting of the following: hafnium oxide, aluminum oxide, scandium oxide, yttrium oxide, titanium oxide, gallium gadolinium oxide and metal oxides of rare earth elements; and (B) vaporize the solid-state metal oxide source in order to make the solid-state metal oxide source become a metal oxide molecular beam and, in a working substrate temperature that is required to achieve an amorphous state of a first metal oxide film, deposit on the base having an amorphous state so as to further fabricate a substrate for MOS transistors.

Growing community of inventors

Hsinchu, Taiwan

Juei-Nai Kwo