Nvidia Corporation

Jue Wu

Jonah Matthew Alben

Sachin Satish Idgunji

Anitha Kalva

Shantanu Sarangi

Sean Jeffrey Treichler

Srihari Raju Vegesna

Anthony Michael Tamasi

Milind Bhaiyyasaheb Sonawane

Padmanabham Patki

Oren Rubenstein

Amit D Sanghani

Mahmut Yilmaz

Chung-Hong Lai

Sailendra Chadalavada

Jonathon E Colburn

Sailendra Chadalavda

Bonita Bhaskaran

Venkat Abilash Reddy Nerallapally

Smbat Tonoyan

Marc R Delvaux

Badrinath Srirangam

Laurent Dahan

Chiang Hsu

Andrew Elias

Sunil Bhavsar

Dan Smith

In various examples, a diagnostic circuit is connected to a target system to automatically trigger the target system to enter a diagnostic mode. The diagnostic circuit receives diagnostic data from the target system when the target system performs a diagnostic operation in the diagnostic mode.

Performing diagnostic operations on a target system

Systems, computer program products, and methods are described herein for automated data retrieval from an integrated circuit (IC). An example system receives an alert indicating a trigger event associated with the IC; extracts, using a scan island (e.g., a partition of the IC that is isolated for data retrieval), data from a plurality of scan chains and a plurality of random-access memories (RAMs) associated with the IC in response to receiving the alert; stores the data in an external non-volatile storage media; and reboots the IC upon storing the data in the external non-volatile storage media. In this way, embodiments of the present invention offer a scalable and secure method for real-time data extraction and processing in the event of an integrated circuit malfunction, improving diagnostics while ensuring cost-effectiveness and data security.

System for automated data retrieval from an integrated circuit for event analysis

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

Leveraging low power states for fault testing of processing cores at runtime

In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment&#x2014;such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

Test system for executing built-in self-test in deployment for automotive applications

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

Test systems for executing self-testing in deployed automotive platforms

Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.

Fault injection architecture for resilient GPU computing

In various examples, one or more components or regions of a processing unit&#x2014;such as a processing core, and/or component thereof&#x2014;may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

A system for testing complex integrated circuits in the field using updated tests, test sequences, models, and test conditions such as voltage and clock frequencies, over the life cycle of the circuit.

Field adaptable in-system test mechanisms

Growing community of inventors

Los Gatos, CA, United States of America

Jue Wu