Massachusetts Institute of Technology

Hewlett-Packard Company

Leland Stanford Junior University

Judy L Hoyt

James F Gibbons

Eugene A Fitzgerald

Dimitri A Antoniadis

Zhi-Yuan Cheng

Theodore I Kamins

David B Noble

Martin P Scott

Stephen Laderman

Clifford A King

Steven Hung

Jason Scott Orcutt

Rajeev J Ram

Milos A Popovic

Charles Holzwarth

Kenneth E Williams

Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices. The ability to reduce gate depletion effects also provides enhanced device current drive.

Method for forming gate electrode with depletion suppression and tunable workfunction

Structures including optical waveguides disposed over substrates having a chamber or trench defined therein, and methods for formation thereof.

Reduction of substrate optical leakage in integrated photonic circuits through localized substrate removal

Gate electrode with depletion suppression and tunable workfunction

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded SiGe(x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed SiGelayer, a thin strained SiGelayer and another relaxed SiGelayer. Hydrogen ions are then introduced into the strained SiGelayer. The relaxed SiGelayer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed SiGelayer remains on the second substrate. In another exemplary embodiment, a graded SiGeis deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

Process for producing semiconductor article using graded epitaxial growth

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si Ge (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si Ge layer, a thin strained Si Ge layer and another relaxed Si Ge layer. Hydrogen ions are then introduced into the strained Si Ge layer. The relaxed Si Ge layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si Ge layer remains on the second substrate. In another exemplary embodiment, a graded Si Ge is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

Semiconductor substrate structure

The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer. The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth. The composition of the third crystalline layer must be such that upon deposition or growth, the third layer substantially continuously binds to the heteroepitaxial structure of the second layer. Subsequent to growth of the at least three layer structure, the structure is processed at temperatures in excess of the growth temperature of the second heteroepitaxial layer. Presence of the third crystalline layer prevents the generation of a substantial amount of misfit dislocations between the first crystalline layer substrate and the second heteroepitaxial layer.

Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x

Several methods are disclosed for minimizing the number of defects or misfit locations in a SiGe layer selectively or non-selectively deposited on a partially oxide masked Si substrate.

Selective and non-selective deposition of Si.sub.1-x Ge.sub.x on a Si

Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625.degree. and 825.degree. C.

Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x Film

Disclosed is a method of welding a temperature-sensing thermocouple to a silicon wafer for sensing the temperature of the wafer during rapid thermal processing using TIG welding and/or electron-beam welding. In one embodiment, a ball of silicon is formed on the bead at one end of a thermocouple by placing the thermocouple on a silicon chip and then melting the silicon chip with a TIG welder. The ball and thermocouple are then placed on the surface of a silicon wafer and the ball and surface are then melted whereby the ball of silicon flows into the silicon wafer. In placing the thermocouple on an edge portion of a silicon wafer, the wafer is supported on a tantalum plate with the edge portion of the wafer extending beyond the plate. A molybdenum sheet is positioned on the top surface of the wafer with the edge portion of the wafer exposed. A TIG arc is established with the molybdenum layer and then the arc is moved to the edge portion of the wafer for melting the silicon. In attaching the thermocouple on the silicon wafer other than on an edge portion, electron-beam welding is employed. An electron beam at low power is focused on the ball of silicon, and then the power of the electron beam is increased while the beam is pulsed so that the ball and adjacent silicon wafer are melted.

Growing community of inventors

Belmont, MA, United States of America

Judy L Hoyt