Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Judson Eugene Veazey

Blaine Douglas Gaither

James J Graham

Michael J Yancey

Darel N Emmot

Russ William Herrell

Patrick Knebel

Benjamin Daniel Osecky

Russell O Craig

Dennis L M Clark

A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state. Upon initiation of a transaction accessing at least one of the cache lines, each of the lines is ensured to be either shared or invalid. During the transaction, in response to an external request for any cache line in the modified, owned, or exclusive state, each line in the modified or owned state is invalidated without writing the line to a main memory. Also, each exclusive line is demoted to either the shared or invalid state, and the transaction is aborted.

Transactional cache memory system

Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.

Memory controller based (DE)compression

A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.

Systems and methods for pushing data

A method is provided for pre-fetching data into a cache memory. A first cache-line address of each of a number of data requests from at least one processor is stored. A second cache-line address of a next data request from the processor is compared to the first cache-line addresses. If the second cache-line address is adjacent to one of the first cache-line addresses, data associated with a third cache-line address adjacent to the second cache-line address is pre-fetched into the cache memory, if not already present in the cache memory.

Multiple address sequence cache pre-fetching

A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory controller performing the memory write without changing ownership to the second device.

Performing a memory write of a data unit without changing ownership of the data unit

A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with all of the cell boards being connected to at least one crossbar switch. The read-latency reducing system includes write-through cache memory on each of the cell boards, a modified line list on each crossbar switch having a list of cache lines that have been modified in the cache memory of each of the cell boards, and a cache coherency directory on each crossbar switch for recording the address, the status, and the location of each of the cache lines in the system. The modified line list is accessed to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line.

System for reducing the latency of exclusive read requests in a symmetric multi-processing system

A compression/decompression (codec) engine is provided for use in conjunction with a fabric agent chip in a multiprocessor computer system. The fabric agent chip serves as an interface between a first memory controller on a first cell board in the computer system and other memory controllers on other cell boards in the computer system. Cell boards in the computer system are interconnected by a system fabric. Memory data read by the first memory controller is compressed by the codec engine prior to being transmitted over the system fabric by the fabric agent chip. Conversely, memory data received over the system fabric by the fabric agent chip is decompressed by the codec engine prior to being provided to the first memory controller. Other fabric agent chips in the computer system may similarly be provided with corresponding codec engines.

Data compression in multiprocessor computers

The present invention provides a system and method for accurately sizing a computer system and its component subsystems. The present invention requires only limited benchmark analysis to design varying subsystem configurations, having varying numbers of users, and accounting for varying ramp-up periods. Moreover, the severe undersizing and oversizing errors inherent in previous systems are avoided without requiring repeated trial and error benchmark trials.

System and method for sizing computer systems with variable ramp-up periods by calculating a throughput for target configuration based on data obtained from a computer subsystem

A method for removing artifacts from a bitmap of image data produced by scanning a halftone image may comprise the steps of: (a) calculating a weighted average intensity value for a target pixel based on a weight factor for the target pixel and on weight factors for neighboring pixels in the bitmap of image data; (b) repeating step (a) for each pixel in the bitmap of image data; and (c) replacing the intensity value of each pixel in the bitmap of image data with the weighted average intensity value for each such pixel.

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Fort Collins, CO, United States of America

Judson Eugene Veazey