Changxin Memory Technologies, Inc.

Juanjuan Huang

Jie Bai

Deyuan Xiao

Weiping Bai

Er-Xuan Ping

Yi Jiang

Lingxiang Wang

Jie Zhang

Dahan Qian

A semiconductor structure includes: a plurality of transistors located in a semiconductor layer; each of the transistors including a semiconductor body extending in a first direction and a gate structure covering at least one side surface of the semiconductor body; the first direction being a thickness direction of the semiconductor layer; a plurality of conductive pillars, each of the conductive pillars being located on a top surface of a corresponding semiconductor body and being in direct contact with the corresponding semiconductor body; a memory structure covering the plurality of conductive pillars.

Semiconductor structure and manufacturing method thereof and memory

A method for forming a memory includes the following operations: a substrate and a semiconductor layer located on the substrate are formed; the semiconductor layer is patterned to form a plurality of first isolation structures and channel regions, each first isolation structure includes a first through hole and a second through hole, and a first isolation pillar located between the first through hole and the second through hole; a first filling layer filling up the first through hole and the second through hole is formed; the first isolation pillar is removed to form a third through hole located in the first filling layer; a barrier layer filling up the third through hole is formed; the channel regions are exposed by removing the first filling layer; and a gate layer covering surfaces of the channel regions is formed.

Memory and method for forming same

A semiconductor structure and a forming method thereof are provided. The forming method of the semiconductor structure comprises: providing a substrate comprising a first area for forming a P-channel Metal Oxide Semiconductor (PMOS) transistor and a second area for forming an N-channel Metal Oxide Semiconductor (NMOS) transistor; forming a channel layer on the surface of the first area of the substrate; adjusting the oxidation rate of the channel layer to reduce the difference between the oxidation rate of the channel layer and the oxidation rate of the substrate; and oxidizing the surfaces of the channel layer and the second area of the substrate to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second area of the substrate.

Semiconductor structure having PMOS transistor with a channel layer and forming method thereof

A semiconductor structure and a method for manufacturing same are provided. The semiconductor structure includes: a doped conductive layer, doped with dopant ions; a metal conductive layer, located above the doped conductive layer; a nitrogen-containing dielectric layer, located above the metal conductive layer; a first molybdenum nitride layer, located between the doped conductive layer and the metal conductive layer and configured to be electrically connected to the doped conductive layer and the metal conductive layer; and a second molybdenum nitride layer, located between the metal conductive layer and the nitrogen-containing dielectric layer, where an atomic ratio of nitrogen atoms in the second molybdenum nitride layer is greater than an atomic ratio of nitrogen atoms in the first molybdenum nitride layer.

Semiconductor structure and method for manufacturing same

A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed in embodiments of the present disclosure. The method of manufacturing a semiconductor includes: providing a base; and forming an electrical contact layer, a bottom barrier layer, and a conductive layer that are sequentially stacked on the base, where a material of the conductive layer includes molybdenum.

Method of manufacturing semiconductor structure and semiconductor structure

A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.

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Hefei, China

Juanjuan Huang