Texas Instruments Corporation

Juanita DeLoach

Haowen Bu

Jiong-Ping Lu

Freidoon Mehrad

Shashank Sureshchandra Ekbote

Yaw S Obeng

Lindsey H Hall

Lance Stanford Robertson

Donald S Miles

Brian Ashley Smith

Troy A Yocum

Brian M Trentman

Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

Nickel silicide formation for semiconductor components

The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.

Method for forming a metal silicide

A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Method of manufacturing metal silicide contacts

The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes forming fluorine containing regions () in the source/drain regions () employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer () over the substrate () and fluorine containing regions (), and reacting the metal layer () with the fluorine containing regions () to form metal silicide regions () in the source/drain regions ().

Method for manufacturing a semiconductor device containing metal silicide regions

The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layerand a hardmask layerlocated over the substratewith plasma, trimming the photoresist layerwith a plasma to create an exposed portionof the hardmask layer, removing the exposed portionwith a plasma to create a trench guide opening, and creating a trenchthrough the trench guide openingwith a plasma.

In situ hardmask pullback using an in situ plasma resist trim process

In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

Growing community of inventors

Plano, TX, United States of America

Juanita DeLoach