Micron Technology Incorporated

Westhold Corporation

Juane Li

Jiangli Zhu

Fangfang Zhu

Ning Chen

Chih-Kuo Kao

Jason Duong

Seungjune Jeon

Ying Yu Tai

Shu Lin

Keke Liu

Khaled Ahmed Sabry Abdel-Ghaffar

Tingjun Xie

Yang Liu

Michael Winterfeld

Aaron Lee

Zhenming Zhou

Yu-Chung Lien

Sead Zildzic, Jr

Yueh-Hung Chen

A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.

Efficient periodic backend refresh reads for reducing bit error rate in memory devices

A method for tracking open blocks in a memory device includes partitioning, by a memory sub-system controller, a storage region in the memory device into a plurality of channels, each channel including a plurality of planesets, and each planeset comprising a plurality of blocksets. The method further includes distributing evenly between the plurality of channels a plurality of active zones ready for a write operation. Each active zone includes one or more open blocks. The method further includes sending, by the memory sub-system controller, an open block message to a controller in the memory device, the open block message including channel identifying information, planeset identifying information, and blockset identifying information. The channel identifying information, the planeset identifying information, and the blockset identifying information collectively identify one or more open blocks ready for a write operation in the memory device.

Open block management in memory devices

A stripe-based command pertaining to a set of host data items at management units (MUs) of a memory sub-system configured to support non-stripe based commands is received. A set of operations to be executed at the MUs based on the stripe-based command is determined. The set of operations include one or more first operations associated with the set of host data items, the one or more first operations having a first type, and one or more second operations associated with the set of host data items, the one or more second operations having a second type. A first set of commands corresponding to the one or more first operations and a second set of commands corresponding to the one or more second operations is executed.

Enabling stripe-based operations for error recovery at a memory sub-system

A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page. The processing device further performs a second media scan operation with respect to a plurality of memory pages addressable by the mandatory wordline, wherein each page of the plurality of memory pages is contained by the respective management unit, and responsive to determining that a value of the data state metric of a memory page of the plurality of memory page addressable by the mandatory wordline satisfies the specified condition, performs a second media management operation with respect to the management unit containing the memory page.

Reducing bit error rate in memory devices

A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.

Dynamic partition command queues for a memory device

A request to write host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination of a first status associated with the host data is made. The redundancy metadata associated with the host data is updated to indicate at least the first status associated with the host data. A memory access operation is performed to write the host data and the updated redundancy metadata to the memory device.

Tracking host-provided metadata in a memory sub-system

Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

Memory device with fast write mode to mitigate power loss

Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.

Cryptographic key management

A system can include a memory device and a processing device coupled with the memory device. The processing device can receive, from a host system, a command of a type; determine a weighted count of the command according to the type of the command; track, based on the weighted count, a first count of commands of the type; determine whether the first count of commands of the type satisfies a threshold criterion for commands of the type; and responsive to determining that the first count of commands of the type satisfies the threshold criterion, transmit a notification to the host system to refrain from transmitting commands of the type.

Concurrent command limiter for a memory system

A die command from a requestor is received. The die command into a die command queue is stored. The die command from the die command queue into a plurality of partition commands is partitioned. The plurality of partition commands into one of a first plurality of partition command queues or a second plurality of partition command queues is mapped. The partition command of the first plurality of partition command queues or the second plurality of partition command queues is issued to a command processor to be applied to the one or more memory devices.

Partition command queues for a memory device

Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT). In one embodiment, a method for joint decoding includes, in part, obtaining a sequence of encoded symbols, wherein the sequence of encoded symbols is generated through GFT, jointly decoding the sequence of encoded symbols using an iterative soft decision decoding algorithm to generate a decoded sequence, transforming the decoded sequence to generate a plurality of cyclic codewords, and decoding the plurality of cyclic codewords to generate a plurality of decoded information symbols.

Storage error correction using cyclic-code based LDPC codes

A partition command from one of a plurality of write partition command queues or a plurality of read partition command queues is received. The received partition command is issued to a command processor of the sequencer component to be applied to one of the one or more memory devices. Responsive to receiving the partition command of the plurality of write partition command queues, whether a timeout threshold criterion pertaining to the plurality of read partition command queues is satisfied is determined. Responsive to determining that the timeout threshold criterion pertaining to the plurality of read partition command queues is not satisfied, whether a write threshold criterion pertaining to the plurality of write partition command queues is satisfied is determined. Responsive to determining that at least one of the timeout threshold criterion pertaining to the plurality of read partition command queues or the write threshold criterion pertaining to the plurality of write partition command queues is satisfied, partition commands of the plurality of read partition command queues is received.

Reduce read command latency in partition command scheduling at a memory device

A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.

A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.

Growing community of inventors

Milpitas, CA, United States of America

Juane Li