Integrated Device Technology, Inc.

Juan Qiao

Zhuyan Shao

Qichang Wu

Zhongyuan Chang

Pengfei Hu

Shuo Liu

A divider can include a phase selection circuit that switches between a plurality of phase-separated clock signals in response to a fractional control signal to form a selected clock signal, the selected clock signal being utilized to generate a second clock signal; and a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the transition control signal indicating when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal.

High frequency fractional-N divider

A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.

Overclocking with phase selection

A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals; quantizing a spread spectrum profile associated with the spread spectrum parameter; mapping the quantized profile; generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal; dividing a phase signal of the plurality of phase signals with the integer control signal; synchronizing the divided phase signal using the phase control signal; and providing a reference clock for a spread spectrum clock generator based on the synchronizing.

Digital spread spectrum method based on precise phase delta-sigma algorithm

A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.

High speed hybrid structure counter having synchronous timing and asynchronous counter cells

A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.

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Shanghai, China

Juan Qiao