International Business Machines Corporation

Juan M Casas, Jr

Brian Frank Veale

Basu Vaidyanathan

Keerthi B Kumar

Nikhil Hegde

Shailaja Mallya

Arnold Flores

Amanda A Liem

Saurabh Nath Sharma

Caleb Russell Olson

Andre Laurent Albot

Michael Passaloukos

Method, computer program product, and computer system are provided. A first migration of a running logical partition (LPAR) is performed from a first-generation computer to a second-generation computer. Availability of a facility differs between the first- and second-generation computers. Upon completion of the first migration, an operating system of the running LPAR detects whether a required facility in use on the first-generation computer is available on the second-generation computer. Operating system takes an action to continue an orderly execution of the LPAR, the operating system, and threads of an application in the LPAR depending on the availability of the required facility. A second migration is performed of the running LPAR from the second-generation computer back to the first-generation computer. The required facility is available on the first-generation computer. The operating system restores access to threads of the application to the required facility.

Disabling a processor facility on a new processor generation without breaking binary compatibility

A processor may receive a software fix package. The processor may apply an interim software code fix of the software fix package to software of a device, where the interim software code fix includes adjusting one or more tunable computing parameters to one or more first values. The processor may identify that a reboot of the device is recommended for application of a permanent code fix of the software fix package. The processor may identify that the device was not rebooted after receipt of the software fix package. The processor may determine that a dynamic reconfiguration event has taken place. The processor may apply, automatically, one or more second values for the one or more tunable computing parameters associated with the interim software code fix of the software fix package.

System tuning across live partition migration

In an embodiment, a guest operating system (OS) running on a virtual machine (VM) detects a VM migration, where the embodiment comprises storing, by the guest OS, a VM identifier (VMID) provided by the VM and a first host identifier (HID) provided by a host computer system in a computer memory. The embodiment also comprises determining, by the guest OS, that the VM performs migrations that are transparent to the guest OS. The embodiment further comprises detecting, by the guest OS, that the VM has been migrated based on a comparison of the first HID to a second HID provided to the guest OS in response to an HID request from the guest OS.

Virtual machine migration detection by a hosted operating system

For a process of an operating system, it is detected that a live migration has occurred, the live migration comprising a change in a hardware characteristic of a computer system on which the process executes. A first message is broadcast to a set of processors, the first message causing each processor in the set of processors to enter a waiting state. While each of the set of processors is in the waiting state, a portion of a set of program instructions of the operating system is modified.

Operating system code patching during live migration

A system and computer program product are provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.

Timer placement optimization

A method is provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.

Systems and computer program products for lock tracing at a component level are disclosed. The one or more embodiments of the invention include computer program instructions for associating one or more locks with a component of the operating system; initiating lock tracing for the component; and instrumenting the component-associated locks with lock tracing program instructions in response to initiating lock tracing. The locks are selected from a group of locks configured for use by an operating system and individually comprise locking code. The component lock tracing may be static or dynamic.

Component lock tracing by associating component type parameters with particular lock instances

Methods for lock tracing at a component level. The method includes associating one or more locks with a component of the operating system; initiating lock tracing for the component; and instrumenting the component-associated locks with lock tracing program instructions in response to initiating lock tracing. The locks are selected from a group of locks configured for use by an operating system and individually comprise locking code. The component lock tracing may be static or dynamic.

Growing community of inventors

Round Rock, TX, United States of America

Juan M Casas, Jr