Analog Devices,inc.

Alpha and Omega Semiconductor International LP

Juan Luo

Javier Alejandro Salcedo

David J Clarke

Gavin Patrick Cosgrave

Stephen Denis Heffernan

John Twomey

Kieran K Heffernan

Brian B Moane

Seamus Murnane

Shekar Mallikarjunaswamy

James Zhao

A transient voltage suppressing device includes a plurality of fingers arranged laterally along a major surface of an epitaxial layer. The plurality of fingers includes fingers of a first type and fingers of a second type. The first type and second type of fingers each include a silicon controlled rectifier (SCR) region and a junction diode region. The plurality of fingers of the second type are conductively coupled together by a second metal layer disposed over top a first metal layer and electrically insulated from the first metal layer. The first metal layer conductively couples the SCR region and junction diode region of the first type of finger.

Low capacitance two channel and multi-channel TVS with effective inter-connection

Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure. Additionally, the clamp device includes a first p-type active region and a first n-type active region in the first p-type well region and electrically connected to a first terminal of the clamp device. Furthermore, the clamp device includes a second p-type active region and a second n-type active region in the second p-type well region and electrically connected to a second terminal of the clamp device. The n-type isolation structure is in a p-type region of a semiconductor substrate, and electrically isolates the first and second p-type well regions from the p-type substrate region. The clamp device further includes a blocking voltage tuning structure positioned between the first and second n-type active regions.

Apparatus and methods for transceiver interface overvoltage clamping

Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Junction-isolated blocking voltage structures with integrated protection structures

An apparatus for transceiver signal isolation and voltage clamp from transient electrical events includes a bi-directional protection device comprising a bipolar PNPNP device assembly, a first parasitic PNPN device assembly, and a second parasitic PNPN device assembly. The bipolar PNPNP device assembly includes an NPN bi-directional bipolar transistor, a first PNP bipolar transistor, and a second PNP bipolar transistor, and is configured to receive a transient voltage signal through first and second pads. The first and second pads are electrically connected to the PNPNP device assembly through emitters of the first and second PNP bipolar transistors. The bipolar PNPNP device assembly is electrically connected to a first parasitic PNPN device assembly comprising a parasitic PNP bipolar transistor and a first parasitic NPN bipolar transistor. The bipolar PNPNP device assembly is further connected to a second parasitic parasitic PNPN device assembly comprising the parasitic PNP bipolar transistor and a second parasitic NPN bipolar transistor. The base of the parasitic PNP bipolar transistor is connected to the substrate of the transceiver through a resistor to prevent triggering and breakdown of the first and second parasitic PNPN device assemblies.

Apparatus for transceiver signal isolation and voltage clamp

Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same

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San Jose, CA, United States of America

Juan Luo