Dell Products Inc.

American Megatrends, Inc.

Juan Francisco Diaz

Anand Prakash Joshi

Wei G Liu

Dirie N Herzi

Anh Dinh Luong

Robert J Volentine

Murali Manohar Shanmugam

Richard Holmberg

Timothy Michael Lambert

Elie Antoun Jreij

Charles Terrence Perusse, Jr

Po-Yu Cheng

William A Moyes

Jayanth Raghuram

Samer El-Haj-Mahmoud

Christopher H McFarland

A microcode update system includes at least one memory device having a code region and a data region, and a microcode update engine that receives a microcode update, and writes the microcode update to the data region of the at least one memory device. Subsequent to writing the microcode update to the data region of the at least one memory device, the microcode update engine utilizes initialization code in the code region of the at least one memory device to perform initialization operations. During a microcode update portion of the initialization operations, the microcode update engine identifies the microcode update in the data region of the at least one memory device, and performs microcode update operations using the microcode update in the data region of the at least one memory device.

Microcode update system

A boot process security system includes a processing system including a plurality of registers, and at least one memory system that includes instructions that, when executed by the processing system, cause the processing system to provide a BIOS. During a Driver eXecution Environment (DXE) sub-process that is included in a boot process and that occurs prior to passing control of the boot process to any third-party drivers, the BIOS programs at least one of the plurality of registers in order to configure at least one secure subsystem. The BIOS then verifies, during the boot process, that the at least one secure subsystem has been configured to provide a predetermined configuration, and locks the at least one secure subsystem. The BIOS then confirms that the at least one secure subsystem has been locked prior to passing control of the boot process to any third-party drivers.

Boot process security self-check system

A method includes storing basic input/output system (BIOS) firmware instructions at a first flash memory device included at an information handling system. The BIOS firmware includes an initial boot block. BIOS data is stored at a second flash memory device. A baseboard management controller validates instructions included at the initial boot block.

Method and apparatus for validating BIOS firmware using a baseboard management controller

An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.

Adjustable performance boot system

An information handling system includes a memory with a cache, and a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code. The pre-OS code sets up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, sets up a page attribute table (PAT) with an entry to define a second memory type for the memory region, disables the PAT, and pass execution by the processor to the boot loader code. The first memory type specifies a first cacheability setting on the processor for data from the memory region, and the second memory type specifies a second cacheability setting on the processor for data from the memory region.

System and method for providing fine-grained memory cacheability during a pre-OS operating environment

A violation of a firmware access rule is detected, and an entry is generated at a log file stored at a baseboard management controller, the entry identifying the violation. In an embodiment, detecting the violation is in response to receiving a system management interrupt at an information handling system.

Method for logging firmware attack event and system therefor

A method and system are provided for updating an utilizing the contents of a non-essential region in a memory device in a computer system. A computer program is utilized to build an image file. The image file may include program code and data for operating a computer system. The image file includes an essential region for storing program code required to boot the computer system and a non-essential region for storing program code and data which is not required to boot the computer system. The non-essential program code may include graphics data, a language module, or diagnostic tools for the computer system. After building the image file, the image file is then copied to a memory device in the computer system. Finally, only the non-essential region in the memory device is updated. A method may also be utilized to execute program code contained in the non-essential region prior to executing program code contained in the essential region.

Method, system, and computer readable medium for updating and utilizing the contents of a non-essential region of a memory device

A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.

Processor interrupt command response system

A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory.

Methods and media for writing data to flash memory

A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

Synchronizing processors when entering system management mode

A method of using BIOS information can include exporting first BIOS information from a first information handling system. The method can further include initiating a boot sequence for the second information handling system and importing second BIOS information into a second information handling system after initiating the boot sequence and before initiating an operating system, wherein the second BIOS information is associated with the first BIOS information. The method can further include initiating an operating system of the second information handling system after importing the second BIOS information. The first and second BIOS information may be the same, or the second BIOS information may be derived from the first BIOS information. The first and second information handling systems may be the same or different. In one embodiment, the first BIOS information can be translated into a text file for editing before using the second BIOS information during a boot sequence.

Methods of using bios information when booting information handling systems and machine-executable code for carrying out the methods

Methods and systems are provided for recovering configuration data in a computer system. According to one method, a device is selected as a current device. A first map location is retrieved from a layout of present configuration data stored in a computer system. Next, a second map location is retrieved from a layout of updated configuration data stored in the computer system for the current device. A determination is then made as to whether the first map location matches the second map location for the current device. If it is determined that the first map location matches the second map location for the current device, then the next hardware device in the set of devices is selected as the current device. If it is determined that the first map location does not match the second map location for the current component, then the present configuration data is copied from the first map location to the second map location in an NVRAM, the present configuration data is erased from the first map location in the NVRAM, and the next hardware device in the set of devices is selected as the current device.

Method and system for recovering the configuration data of a computer system

A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, each disabled logical processor branches to the hard coded interrupt service routine. The interrupt service routine can be written to read only memory because the context, current instruction, and return state of the disabled logical processor are known, and the disabled logical processor will not need to write to system memory during the execution of the interrupt service routine. Following the handling of the interrupt by another logical processor of the computer system, each disabled logical processor returns to the halt state.

System and method for processing an interrupt in a processor supporting multithread execution

A method and computer system are provided for recovering program code in a memory device. A determination is made as to whether current program code stored in a memory device in the computer system is valid. The current program code may be current BIOS code for the computer system. If it is determined that the current program code is invalid, code stored in the memory device is executed to copy an image file from a storage device to a main memory in the computer system. The image file includes recovery program code for the memory device. The current program code in the memory device is then updated with the recovery program code from the main memory. Prior to updating the current program code, a flag is set indicating that the current program code needs to be updated. A boot of the computer system is then initiated from the image file and upon detecting the flag, the boot of the computer system is interrupted. While the current program code in the memory device is being updated with the recovery program code, status messages related to the ongoing update may be displayed on a video display device in the computer system.

Growing community of inventors

Round Rock, TX, United States of America

Juan Francisco Diaz