Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Agency for Science, Technology and Research

Alsephina Innovations Inc.

Juan Boon Tan

Wanbing Yi

Yi Jiang

Curtis Chun-I Hsieh

Danny Pak-Chum Shum

Fan Zhang

Ramasamy Chockalingam

Bei Chao Zhang

Bharat Bhushan

Wei Liu

Soh Yun Siah

Yeow Kheng Lim

Hai Cong

Benfu Lin

Eng Huat Toh

Wuping Liu

Shyue Seng Tan

Lup San Leong

Huang Liu

Alex See

Liang Choo Hsia

Xinshu Cai

Chim Seng Seet

Tae Jong Lee

John Leonard Sudijono

Kiok Boone Elgin Quek

Luke G England

Sunil Kumar Singh

Khee Yong Lim

Wei Lu

Shaoqiang Zhang

Wenhe Lin

Kheng Chok Tee

Young Way Teh

Feng Chen

Dong Kyun Sohn

Xuan Anh Tran

Kangho Lee

Ian D Melville

Lanxiang Wang

Jeoung Mo Koo

Tze Ho Simon Chan

Yongshun Sun

Mahesh Bhatkar

Shunqiang Gong

Wei-Hui Hsu

Wei Shao

Jianxun Sun

Ee Jan Khor

Daxiang Wang

Kai Kang

Alan Cuthbertson

Soon Ee Neoh

Haifeng Sheng

Chin Chuan Neo

Xiaodong Li

Shan Gao

Laiqiang Luo

Tu Pei Chen

Tupei Chen

Pak-Chum Danny Shum

Bhushan Bharat

Neha Nayyar

Yong Kong Siew

Ranjan Rajoo

Shijie Wang

Tong Qing Chen

Peter Chew

Eswar Ramanathan

Francis YongWee Poh

Kin Wai Tang

Fook Hong Lee

Suryanarayana Kalaga

Vincent Ho

Boo Yang Jung

Arthur Ang

Danny PakChum Shum

Zhehui Wang

Bo Tao

Cing Gie Lim

Hyunwoo Yang

Kam Chew Leong

Liang-Choo Hsia

Sung Mun Jung

Weining Li

Pinghui Li

Bong Woong Mun

Yang Hong

Lei Wang

Xuesong Rao

Kai Chong Chan

Lulu Peng

Huajun Liu

Jian Sun

Aaron Chen

Kho Liep Chok

Fang Hong Gn

Zhiqiang Teo

Dong Wang

Jens Oswald

Structures for a resistive random-access memory element and methods of forming a structure for a resistive random-access memory element. The structure comprises an interlayer dielectric layer including a first trench having a sidewall and a second trench having a sidewall adjacent to the sidewall of the first trench. The structure further comprises a first layer on the sidewall of the first trench, a second layer inside the second trench, and a third layer on the sidewall of the second trench. The first layer comprises a first metal, the second layer comprises a second metal, and the third layer comprises a dielectric material. The third layer includes a portion positioned between the first layer and the second layer.

Resistive random-access memory elements with lateral sidewall switching

The present disclosure relates to semiconductor structures and, more particularly, to capacitor structures and methods of manufacture. The structure includes: an airgap provided within a dielectric material; an insulator material across a top of the airgap and on a surface of the dielectric material; and a capacitor provided within the dielectric material and lined with the insulator material.

Capacitor and airgap structure

According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

Programmable interposer using RRAM platform

The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. More particularly, the present disclosure relates to a method of forming a sensor device and a bond pad in the same dielectric region. The present disclosure also relates to the semiconductor devices formed by the method disclosed herein.

Method of forming a sensor device having moisture sensitive dielectric layer with integrally formed projections

A semiconductor memory device is provided. The memory device includes a first electrode, a resistive layer, and a second electrode. The resistive layer is arranged over the first electrode. The second electrode is arranged over the resistive layer. The second electrode includes a lower surface and an extension extending from under the lower surface. The extension is at least partially arranged within the resistive layer.

Semiconductor memory devices having an electrode with an extension

A device may include a first conductive element and an interlevel dielectric arranged over the first conductive element. The device may further include a dual damascene opening including a first end, a second end, and sidewalls extending between the first and second ends, the sidewalls extending through the interlevel dielectric. A metal-insulator-metal (MIM) stack may line the dual damascene opening. The MIM stack may include a first conductive liner lining the sidewalls and the second end of the dual damascene opening, an insulator layer lining the first conductive liner, and a second conductive liner lining the insulator layer. A first metal interconnect may be disposed in and filling the dual damascene opening lined with the MIM stack.

Metal-insulator-metal capacitor (MIMCAP) and methods of forming the same

A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

Three electrode capacitor structure using spaced conductive pillars

Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

SRAM bit cells with three-dimensional integration

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

Memory devices and methods of forming the same

A memory device may be provided. The memory device may include a first electrode including a first side surface and a second side surface opposite to the first side surface; a passivation layer arranged laterally alongside the first side surface of the first electrode; a switching layer arranged laterally alongside the passivation layer; and a second electrode arranged along the switching layer.

Memory devices and methods for fabricating memory devices

The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. A plurality of electrodes and a bond pad are formed in a dielectric region. A passivation layer is formed on each electrode in the plurality of electrodes and the bond pad. A barrier layer is formed on the passivation layer. A plurality of trenches are formed to extend through the barrier layer and into the dielectric region. Formation of the trenches simultaneously exposes an upper surface of the bond pad. A moisture sensitive dielectric layer is formed on the barrier layer. Formation of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes.

Method of forming a sensor device

Structures for a resistive memory element and methods of forming a structure for a resistive memory element. A resistive memory element has a first electrode, a second electrode partially embedded in the first electrode, a third electrode, and a switching layer positioned between the first electrode and the third electrode. The second electrode includes a tip positioned in the first electrode adjacent to the switching layer and a sidewall that tapers to the tip.

Resistive memory elements with an embedded heating electrode

The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides that converge at a top of the first electrode, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.

Memory devices and method of forming the same

A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.

Galvanic isolation using isolation break between redistribution layer electrodes

A semiconductor device includes a first insulating layer; a second insulating layer arranged over the first insulating layer; a memory structure arranged within a memory region and including a resistance changing memory element within the first insulating layer; and a logic structure arranged within a logic region. In the memory region, the first insulating layer may contact the second insulating layer and in the logic region, the semiconductor device may further include a stop layer arranged between the first insulating layer and the second insulating layer.

Semiconductor devices and methods of forming semiconductor devices with logic and memory regions insulation layers

Growing community of inventors

Singapore, Singapore

Juan Boon Tan