International Business Machines Corporation

University of Michigan

Juan-Antonio Carballo

Ivan Vo

Kevin John Nowka

Jeffrey L Burns

Seung-moon Yoo

David William Boerstler

Gary Dale Carpenter

Seung-Moon Yoo

Hung Cai Ngo

Fadi Hikmat Gebara

Li Shi

Stephen W Director

An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone. The complexity of processing blocks within the receiver and/or transmitter are adjusted in conformity with one or more selection signals and an operating voltage level is selected in accordance with the requirements of the reduced complexity circuit. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input.

Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage

A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Digital transmission circuit and interface providing selectable power consumption via multiple weighted driver slices

Power reduction in links, such as transmitters and receivers, based upon global decisions such as the data transmission frequencies, communications media, and traffic types associated with links, is disclosed. In particular, embodiments take advantage of high-level decisions by reconfiguring internal circuits of transmitters and receivers of links to reduce power consumption. At the global level, a decision determines the links that are active, the data frequency at which the links operate, and the media through which the links transmit the data. At the local level, the links receive the decisions and reconfigure circuitry automatically to minimize power based upon the decisions. In some embodiments, the links may receive the decisions in the form of power modes. In further embodiments, the links may receive settings such as on/off settings, data frequency settings, and traffic/media settings, the combination of which indicates power modes.

Global management of local link power consumption

A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices

A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.

Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation

Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by the receivers may be reduced. Embodiments identify situations in which spread spectrum clocking is unnecessary and may adapt the CDR loop to operate with less power consumption by, e.g., reducing the operating frequency of CDR circuits. For instance, some embodiments employ a flywheel circuit, incorporated into many spread spectrum CDR loops to accelerate adjustments to a sampling clock, to determine when spread spectrum signals are not being encountered. A loop latency controller may then, advantageously, reduce power consumption by reducing frequencies of operation and voltages, and merging or simplifying stages.

Methods and arrangements for link power reduction

Methods, and arrangements for power reduction in links, such as transmitters and receivers, based upon global decisions such as the data transmission frequencies, communications media, and traffic types associated with links, are disclosed. In particular, embodiments take advantage of high-level decisions by reconfiguring internal circuits of transmitters and receivers of links to reduce power consumption. At the global level, a decision determines the links that are active, the data frequency at which the links operate, and the media through which the links transmit the data. At the local level, the links receive the decisions and reconfigure circuitry automatically to minimize power based upon the decisions. In some embodiments, the links may receive the decisions in the form of power modes. In further embodiments, the links may receive settings such as on/off settings, data frequency settings, and traffic/media settings, the combination of which indicates power modes.

A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Method of transparently reducing power consumption of a high-speed communication link

A system for designing a communication link for use in a data processing system, includes a parameter generator and an internal link model. The parameter generator allows a user to specify a first set of link parameters. The generator derives a set of internal parameters from the first set of parameters. The internal link model, which includes a set of configurable link cells, receives the internal parameters and instantiates each link cell based on the internal parameters. The system further includes a channel simulator or similar means for modeling a bit error rate (BER) of the instantiated communication link and may further include an estimator of the link's area and power consumption. In an embodiment that protects the intellectual property associated with the internal model from the system user, the parameter generator prevents the user from directly accessing the internal parameters and the generic link model.

Customer controlled design of a communication system

A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices

A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.

Method and apparatus for measuring communications link quality

A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at GHz frequencies. The digital signal is processed by inverters and interpolators which may be readily matched in size and functional characteristics by close proximity placement on integrated circuits. An inverted and first delayed version of the original digital signal is applied to both inputs of a first interpolator, to generate at the output of the interpolator the complement of the digital signal as delayed by the first delayed and the delay introduced by the interpolator. The inverted and first delayed digital signal is inverted and second delayed by a second matching inverter and applied as one input to a second interpolator. The second input of the second interpolator is the original digital signal. The output of the second interpolator is the digital signal delayed by a corresponding combination of the first delay and the delay introduced by the second interpolator. When the first and second interpolators are matched, in the manner of the first and second inverters, the two interpolator outputs provide the digital signal and its complement with substantially no skew and matching increments of delay.

Method and apparatus for generating non-skewed complementary signals through interpolation

Method and system are provided for providing constraint-based guidance to a designer to support the application of useful constraint-based heuristics in complex collaborative design, thus reducing late conflicts and facilitating their resolution when they happen. The invention can be applied to any collaborative problem-solving task such as a collaborative engineering activity or the design of corporate strategies. In the method and system, designers receive constraint-based feedback that enables them to apply constraint-based heuristics that consider the simultaneous effect of all design constraints.

Growing community of inventors

Austin, TX, United States of America

Juan-Antonio Carballo