Samsung Electronics Co., Ltd.

Ju-yun Jung

Hyun-Joong Kim

Sun-Young Lim

Dong-Yang Lee

Bu-Il Jung

Min-Yeab Choo

Sang-Uhn Cha

Ho-Young Song

Hoi-ju Chung

Do-Geun Kim

Hyuk Soo Han

Mi-Kyoung Park

Young-Jin Cho

Sung-Ho Cho

Won-hyung Song

Ho-young Song

Sang-hoon Shin

Yoo-Jung Lee

Jang Seok Choi

Duk-Sung Kim

Sung-yong Seo

Soo-Woong Ahn

Seong-Jin Lee

Kyo-min Sohn

Bu-il Jung

Gi-won Oh

Soo-Hyeong Kim

Hee-Joo Choi

Hoki Kim

Ha-Ryong Yoon

Soo-hyeong Kim

Hae-suk Lee

Han-vit Jeong

Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

Memory device and memory system performing request-based refresh, and operating method of the memory device

A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.

Memory system capable of re-mapping address

A memory swap operation comprises writing information about a process in which a page fault occurred, into a temporary memory using a processor of a host, copying a page in which the page fault occurred, from a memory device recognized as a swap memory into a main memory of the host, and after completing the copying of the page, resuming the process in which the page fault occurred, using the information about the process, written in the temporary memory.

Method of controlling memory swap operation and data processing system using same

A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.

Memory address remapping system, device and method of performing address remapping operation

A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines, and control logic configured to control execution of a post package repair operation by the memory device. The control logic includes a PPR control circuit that programs a bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.

Memory device performing post package repair (PPR) operation

A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

Memory device having a shareable error correction code cell array

A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.

Semiconductor memory device, memory system including the same, and method of operating the same

A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.

Memory device and computing system including the same

A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.

Method of repairing a memory device and method of booting a system including the memory device

The stacked semiconductor device including a first chip, a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes and including a first memory and a memory controller that are each controlled by the first chip, and a second memory positioned on the second chip and connected to a plurality of second penetration electrodes and controlled by the memory controller.

Stacked semiconductor device and method of manufacturing the same

Growing community of inventors

Hwaseong-si, South Korea

Ju-yun Jung