Hynix Semiconductor Inc.

Ju-Young Seo

Chang-Hyuk Lee

Hi-Hyun Han

Chae-Kyu Jang

In a semiconductor memory device which performs a repair method of replacing a repair target word line and one adjacent word line at the same time by a repair operation through an efficient decoding operation for selecting a repair target address, a test operation of enabling only a word line corresponding to a cell coupled to a bit line or a bit line bar is stably performed.

Semiconductor memory device

A semiconductor memory device includes a source signal generator configured to generate a source signal having a predetermined pulse width in response to a command signal, and a column selection signal generator configured to generate a column selection signal by controlling a pulse width of the source signal according to a voltage level of an external supply voltage.

Semiconductor memory device and driving method thereof

A circuit for controlling an internal voltage is provided. The circuit for controlling an internal voltage, comprising: a level detector configured to detect a voltage level of a core voltage to generate a core voltage level detection signal; a release controller configured to generate a release control signal according to the core voltage level detection signal; and a core voltage release driver configured to release the core voltage according to the release control signal.

Circuit and method for controlling internal voltage

A sense amplifier control circuit for a memory device is provided. The sense amplifier control circuit for a memory device including: a level detection unit configured to generate a level detection signal by detecting a core voltage level in an active operation interval; and a control unit configured to generate a pulse signal to control a sensing start time of a bit line detection signal by varying a delay time according to the level detection signal.

Sense amplifier control circuit for semiconductor memory device and method for controlling sense amplifier control circuit

A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Semiconductor memory device for driving a word line

A sense amplifier control unit include: a control unit that detects a variation in the level of an external voltage and outputs a delay time selection signal on the basis of the result of the detection. A variable delay unit delays an active signal by a delay time corresponding to the delay time selection signal and outputs the delayed signal. A driving signal generating unit outputs a driving signal according to the output of the variable delay unit. A sense amplifier driver drives a sense amplifier on the basis of the driving signal.

Circuit and method for controlling sense amplifier of a semiconductor memory apparatus

A semiconductor memory over-driving scheme for a semiconductor memory device makes it possible to secure a high-speed sensing operation of a memory sense amplifier, regardless of a change of a power supply voltage. Over-driving efficiency is improved by controlling the discharging time and the drivability using different sized the drivers when the power supply voltage fluctuates while the bit line over-driving operation is performed.

Over-driving circuit in semiconductor memory device

A semiconductor memory device having a bit line sense amplifier supporting an over driving operation includes a voltage divider; a plurality of signal converters; a delay unit; and a drive control signal generator. The voltage divider divides an external voltage to generate a plurality of different voltage levels. The signal converters convert each of the plurality of voltage levels into a corresponding digital signal. The delay unit delays an active signal provided from outside by a delay amount for defining an over driving interval in response to the plurality of digital signals. The drive control signal generator generates a drive control signal for a bit line sense amplifier driver in response to a delayed active signal from the delay unit.

Disclosed is a semiconductor memory device with a reduced write recovery time and an increased refresh period. The semiconductor memory device incorporating a plurality of memory cells therein, including: a bit line sense amplifier (BLSA) array provided with a plurality of bit line sense amplifiers for sensing and amplifying data of the memory cells applied to bit lines; and a BLSA driving control means for overdriving a bit line connected to the bit line sense amplifier in response to an active command, and for overdriving the bit line in response to a precharge command.

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Kyoungki-do, South Korea

Ju-Young Seo