Qualcomm Incorporated

Ju-Yi Lu

Chun-Chen Liu

Chunchen Liu

Shengqiong Xie

Po-Hung Chen

Zhengyu Duan

Oscar Ming Kin Law

Oscar Law

Integrated circuits and methods of manufacturing such circuits are disclosed herein that feature metal line-via matrix insertion after place and route processes are performed and/or completed for the integrated circuit's layout. The metal line-via matrix consists of one or more additional metal lines and one or more additional vias that are inserted into the integrated circuit's layout at a specific point to lower the current and current density through a first conductive path that has been determined to suffer from electromigration, IR-voltage drop, and/or jitter. Specifically, the metal line-via matrix provides one or more auxiliary conductive paths to divert and carry a portion of the current that would otherwise flow through the first conductive path. This mitigates electromigration issues and IR-voltage drop along the first conductive path. It may also help alleviate problems due to jitter along the path.

Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion

A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to connect the dies on the different layers. In some aspects, a power distribution network (PDN) is routed from a first layer through the switches to supply power to at least one other layer, thereby reducing routing congestion on the layers. The switches can be placed around the periphery of an IC package to improve heat dissipation (e.g., by improving heat transfer from the center to the edge of the IC package). The switches can be used for routing test signals and/or other signals between layers, thereby improving test functionality and/or fault recovery.

3D integrated circuit

Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

Uncertainty aware interconnect design to improve circuit performance and/or yield

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San Diego, CA, United States of America

Ju-Yi Lu