Samsung Electronics Co., Ltd.

Ju-Wan Kim

Kyu-Tae Na

Min Soo Kim

Dae-Young Kwak

Il-Woo Kim

Hyong-Soo Kim

Seung-Bae Park

Sung-Jin Kim

Sang-Hoon Lee

Gwan-Hyeob Koh

Young-Hoon Park

Seung-Heon Lee

Myoung-Bum Lee

Hyun-young Kim

Chang-hyun Cho

Ju-Bum Lee

Kyung-Tae Jang

Seung-Mok Shin

Tae-Jong Han

Myoung-Hee Han

Taek-Jung Kim

Shin-Hye Kim

Byung-Keun Hwang

Koong-Hyun Nam

Ji-Youn Seo

Ji-Woon Im

Hyun-Yong Go

Ju-bum Lee

Hyun-kuk Ko

Jue-Goo Lee

Young-Roe Kim

Kyung-Burn Koo

Dong-chan Park

Dong-Geun Na

In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Vertical memory devices and methods of manufacturing the same

An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.

Isolation layer structure, method of forming the same and method of manufacturing a semiconductor device including the same

Method of forming isolation layer structure and method of manufacturing a semiconductor device including the same

A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.

Method of removing an oxide and method of filling a trench using the same

A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.

Method of manufacturing a semiconductor device

A semiconductor memory device for reducing parasitic bit line capacitance and a method of fabricating the same are provided. The semiconductor memory device includes a conductive pad formed on a semiconductor substrate and a first interlayer insulating layer having a first contact hole that exposes the conductive pad. The first interlayer insulating layer is formed on the conductive pad and the semiconductor substrate. Bit line stacks are formed on the first interlayer insulating layer. Bit line spacers are formed from a combination of materials having different dielectric constants on the sidewalls of the bit line stack to reduce the parasitic bit line capacitance. Preferably, the bit line spacers are stack layers including silicon nitride, silicon oxide, and silicon nitride. A second interlayer insulating layer having a second contact hole is formed on the bit line stack. A conductive plug fills the first and second contact holes. A storage electrode of a capacitor is formed on the conductive plug to be connected to the conductive pad.

Semiconductor memory device for reducing parasitic bit line capacitance and method of fabricating the same

A dielectric layer is formed by depositing a first dielectric layer above a semiconductor substrate including recessed regions, etching the first dielectric layer to remove any voids and to lower the aspect ratio of the recessed regions, and depositing a second dielectric layer on the first dielectric layer in the recessed regions. The method is particularly useful when the aspect ratios are high for recessed regions formed between patterns.

Method for forming a dielectric layer

A method and an apparatus for removing particulate contaminant are provided in order to ensure high purity during a tungsten suicide deposition process. The method for removing particulate contaminant in tungsten silicide deposition process using SiH,as silicon source gas and NF,as cleaning gas, includes purging a carrier gas line for an SiH,silicon source gas to remove the contaminant in the chamber and carrier gas line when the carrier gas is supplied with the chamber, and the NF,cleaning gas is supplied to the chamber to form plasma. After a plasma cleaning, the gas line flowing reaction gas responding to the SiH,is purged to remove the contaminant in the chamber and the reaction gas line. As a result, any particulate contaminant is removed or remains at a minimum level that has no effect on the tungsten silicide deposition process.

Filtering technique for CVD chamber process gases

Growing community of inventors

Seongnam-si, South Korea

Ju-Wan Kim