Lattice Semiconductor Corporation

Advanced Micro Devices Corporation

Vantis Corporation

Ju Shen

Om P Agrawal

Cyrus Y Tsui

Albert L Chan

Michael J Wright

Chan-Chi Jason Cheng

Howard H Tang

Rafael Czernek Camarota

San-Ta Kow

Satwant Singh

Jinghui Zhu

Kapil Shankar

Ji Zhao

Roger Spinti

Allan Thomas Davidson

Kuang Chi

Gregg R Josephson

Clement Lee

Hua Xue

Jock F Tomlinson

Roy D Darling

Jason Cheng

Bradley Felton

Bertrand Leigh

Chris West

Mike Ray

Howard Y M Tang

Manish Garg

Jack Tim Wong

Benny Ma

Sam Tsai

Ming C Hsu

Chanchi J Cheng

Jason Chang

Tong-Sheng Wang

Jin Ni

Albert Chen

Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output (SSO) noise data for an electronic device includes collecting hardware data on SSO noise conditions; generating additional data on SSO noise conditions based on the hardware data; and structuring the hardware data and the additional data to form data tables for SSO noise calculations.

Simultaneous switching output noise estimation and reduction systems and methods

Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.

Register data retention systems and methods during reprogramming of programmable logic devices

In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key includes a plurality of data bit values, wherein each data bit value of the security key is associated with a subset of a least three fuses each storing a bit. Each of a plurality of decoders is adapted to retrieve a data bit value of the security key by providing the bit value stored by a majority of the fuses of the associated subset as the data bit value of the security key.

Method and devices for storing a security key using programmable fuses

Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I/O signals to their assigned pin locations; placing unassigned I/O signals to initial I/O pin locations; and performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements.

Input/output placement systems and methods to reduce simultaneous switching output noise

Systems and methods are disclosed herein to provide improved security key techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a method of providing data security for a programmable logic device (PLD) includes programming a plurality of programmable fuses that stores a security key comprising a plurality of data bit values, wherein each data bit value is associated with a respective subset of at least three of the fuses. The security key is retrieved from the fuses using the data bit values stored by each subset of the fuses. An encrypted configuration data bitstream is decrypted using the retrieved security key to obtain an original configuration data bitstream to configure the PLD.

Methods and systems for storing a security key using programmable fuses

Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks and corresponding input/output pins, and configuration memory. The PLD also includes registers adapted to capture output signal values of the input/output pins before a reconfiguration of the programmable logic device and to provide the captured values on the input/output pins during the reconfiguration of the PLD.

Reconfiguration of programmable logic devices

A programmable logic block within a programmable logic device includes at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables. Each interconnected lookup table is adapted to receive input signals from a routing structure and to provide a LUT output signal. At least one of the slices includes a register adapted to register the LUT output signal of a lookup table and at least another of the slices includes fewer such registers than lookup tables.

Programmable logic device with enhanced logic block architecture

Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.

Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks and corresponding input/output pins, and a plurality of configuration memory cells. The configuration memory cells are adapted to store configuration data for configuration of the logic blocks and the input/output blocks. A data port is adapted to provide a clock signal to and receive configuration data from an external memory. A plurality of circuits are adapted to hold the input/output pins in a known logic state during the configuration.

In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.

SERDES with programmable I/O architecture

In one embodiment of the invention, a programmable logic block within a programmable logic device includes: a plurality of lookup tables, each lookup table providing a combinatorial output signal; and a plurality of registers, each register being adapted to register a selected one of the combinatorial output signals, wherein the number of registers is less than the number of lookup tables.

In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.

A programmable logic device includes a plurality of logic blocks. Each logic block includes a plurality of macrocells, with each macrocell being configurable to register a sum of product term output. In addition, the macrocells within each logic block are arranged from a first macrocell to a last macrocell. Each macrocell is associated with a carry-in and a carry-out signal. The macrocells are configured to support a carry cascade such that the carry-out signal from the first macrocell becomes the carry-in signal for the second macrocell, and so on.

Macrocells supporting a carry cascade

A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.

Programmable logic device with enhanced wide input product term cascading

An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.

Growing community of inventors

San Jose, CA, United States of America

Ju Shen