Samsung Electronics Co., Ltd.

Ju-Seon Goo

Hong-Gun Kim

Eun-Kee Hong

Kyu-Tae Na

Jin-Gi Hong

Myeong-Cheol Kim

Soo-Jin Hong

Ju-Bum Lee

Jin-Hwa Heo

Moon-Han Park

Seong-ho Kim

Hae-jeong Lee

Byung-keun Hwang

A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

Method for forming a silicon oxide layer using spin-on glass

Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device. Thus, a planar silicon oxide layer is formed between conductive patterns having a fine interval therebetween without creating a void. In addition, a metal layer pattern, which acts as a conductor in the conductive patterns, can be prevented from being oxidized when the silicon oxide layer is formed.

Method of forming a silicon oxide layer of a semiconductor device and method of forming a wiring having the same

A method of forming a SOG insulation layer of a semiconductor device comprises forming the SOG insulation layer on a substrate having a stepped pattern by using a polysilazane in a solution state, performing a pre-bake process for removing solvent elements of the insulation layer at a temperature of 50 to 350&deg; C., performing a hard bake process for restraining particles from forming at a temperature of 350 to 500&deg; C., and annealing at a temperature of 600 to 1200&deg; C. The method of the invention further includes planarizing the insulation layer between the hard bake process and the annealing step. Also, the hard bake process can be omitted.

Method of forming a spin-on-glass insulation layer

A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane (&lsqb;SiH NH&rsqb;n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 &angst; from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

Method of forming an insulating layer in a trench isolation type semiconductor device

A method of forming a SOG insulation layer of a semiconductor device comprises the steps of forming the SOG insulation layer on a substrate having a stepped pattern using a solution containing a polysilazane in an amount of less than 20% by weight in terms concentration of solid content, performing a pre-bake process for removing solvent ingredients in the insulation layer at a temperature of 50 to 350&deg; C., and annealing at a temperature of 600 to 1200&deg; C. The method of the invention further includes performing a hard bake process at a temperature of about 400&deg; C. between the pre-bake process and the annealing step. Also, the polysilazane is desirably contained in an amount of 10 to 15% by weight.

A method for stabilizing an interlevel dielectric layer formed by a chemical vapor deposition (CVD) process, using electron beams. A CVD oxide layer is formed on a semiconductor substrate. The CVD oxide layer is radiated with electron beams at a temperature of between approximately room temperature and approximately 500.degree. C. for a predetermined time, using an electron beam radiator, to densify the layer.

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Suwon, South Korea

Ju-Seon Goo