Samsung Electronics Co., Ltd.

Ju-Ri Kim

Sung-Chul Park

Seung-Beom Yoon

Weon-Ho Park

Byoung-Ho Kim

Jeong-Uk Han

Hyun-Khe Yoo

Kwang-Wook Koh

Jae-Hwang Kim

Sang-Soo Kim

Chang-Hun Lee

Sung-Ho Kim

Kwang-Tae Kim

Jeong-wook Han

Seung-Jin Yang

Hyun-khe Yoon

A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

Single chip data processing device with embedded nonvolatile memory and method thereof

Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same

An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Electrically erasable programmable read-only memory (EEPROM) device and methods of fabricating the same

In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Non-volatile memory device and methods of forming and operating the same

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Seoul, South Korea

Ju-Ri Kim