National Science Council

Ju-Ming Chou

Jieh-Tsorng Wu

Yu-Tang Hsieh

To reduce the effect of the phase shift error originated from the mismatch of the delay units of the clock generator, we propose to add one more set of averaging amplifiers and averaging impedances, such as resistors, into the circuit of the clock generator. In the clock generator, outputs of all delay units connect to inputs of all averaging amplifiers respectively, and the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers, so as to form a closed loop. When a phase shift error occurs in the delay units, the averaging current through the averaging impedances will decrease the phase shift error in each stage. Specifically, the output impedance of the averaging amplifiers approaches infinite, and thus the resistance of the averaging impedances is relatively small. Therefore almost all signal currents will go through the averaging impedances, and an optimal averaging effect is achieved. In addition, we apply the simple voltage-mode phase interpolation technique to the averaging impedances for better phase resolution and more output phases. Further, utilizing the folding architecture, our proposed clock generator can output high-frequency clock signals at low-frequency operating clock.

Growing community of inventors

Hsinchu, Taiwan

Ju-Ming Chou