Samsung Electronics Co., Ltd.

Ju-Il Choi

Atsushi Fujisaki

Jeonggi Jin

Jin Ho An

Gyuho Kang

Kwang-Jin Moon

Un-Byoung Kang

Ho-jin Lee

Chungsun Lee

Dong-Chan Lim

Ju-Bin Seo

Byung-Lyul Park

Seong-Hoon Bae

Jongho Lee

Jumyong Park

Dongjoon Oh

Hyunsu Hwang

JuBin Seo

Teahwa Jeong

Kwangjin Moon

Junyoung Park

Son-kwan Hwang

Sujeong Park

Su-Jeong Park

Jongho Park

Pil-Kyu Kang

Jeong-Woo Park

In-Young Lee

Ji-soon Park

Dong-chan Lim

Jin-Ho An

Jinho Chun

Kun-sang Park

Son-Kwan Hwang

Yeun-Sang Park

Jae-hyun Phee

Jung-Hwan Kim

Hoonjoo Na

Hyun-Soo Chung

Tae-Seong Kim

Kyu-ha Lee

Heewon Kim

Solji Song

Jaehyung Park

Hoechul Kim

Seongmin Son

Byeongchan Kim

Sechul Park

Hyoju Kim

Yong-hwan Kwon

Tae-Je Cho

Nam-seog Kim

Byung Lyul Park

Tae Hong Min

Kang-Wook Lee

Yun Seok Choi

Cha-Jea Jo

Jae-Hwa Park

Naein Lee

Gilheyun Choi

Seung-Kwan Ryu

Sun-kyoung Seo

Sang-Sick Park

Seok-Ho Kim

Jin-ho Chun

Yonghoe Cho

Chang-Woo Shin

Keum-Hee Ma

Do-Sun Lee

Seong-min Son

Kunsang Park

Hyojin Yun

Woo-Dong Lee

Su-Kyoung Kim

Junyun Kweon

Min-Seung Yoon

Jeong-gi Jin

Myung-Kee Chung

Byunglyul Park

Jisoon Park

Minseung Yoon

Byung-Iyul Park

Joo-Hee Jang

Myeong-soon Park

Hyung-Seok Kim

Hyo-Ju Kim

Jeong-Gi Jin

Sukyoung Kim

Ui-Hyoung Lee

Uihyouong Lee

A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.

Interconnection structure and semiconductor package including the same

Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

Semiconductor package

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Semiconductor device

A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

Semiconductor device and semiconductor package including the same

A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.

A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

Semiconductor packages

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers includes first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips.

Semiconductor package and method of fabricating the same

A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Method of fabricating a semiconductor device

A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

Semiconductor package device

Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

Semiconductor devices and semiconductor packages including the same

A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices

Growing community of inventors

Seongnam-si, South Korea

Ju-Il Choi