Samsung Electronics Co., Ltd.

Hana Micron Inc.

Other

Samsung Electro-mechanics Co., Ltd.

Ace Technology

Ju-Hyung Kim

Jung-Dal Choi

Chung-woo Kim

Jong-Sun Sel

Chang-seok Kang

Sang-Hun Jeon

Sung-Il Chang

Soo-doo Chae

Chang-Seok Kang

Youn-seok Jeong

Jae-Sung Lim

Yoo-Cheol Shin

Jang-Hyun You

Chang-Hyun Lee

Woon-Kyung Lee

Young-Woo Park

Jae-woong Hyun

Jung-dal Choi

Byeong-In Choe

Tea-Kwang Yu

Dek-Gin Yang

Woo-seok Kim

Jae-Sung Sim

Jeong-Hee Han

Hee-soon Chae

Jae-Suk Sung

Jin-Wook Jeong

Won-Woo Cho

Hyouk Lee

Seok-Min Jung

Jeong-Kun Oh

Woon-Phil Kim

Byung-Il Oh

Yong-Hee Lee

Hyun-Joo Kim

Jae-Youb Jung

A medical diagnostic apparatus having a height-adjustable table for animals according to an embodiment of the present invention includes: a table where an animal is placed; a support stand supporting the table such that the table vertically moves and adjusting height of the table to move the table close to a floor; an X-ray detector disposed under the table and coupled to the support stand to move with the table; and an imaging stand spaced from the table, connected to the support stand, and having an X-ray tube for radiating X-rays to the X-ray detector.

Medical diagnostic apparatus having height-adjustable table for animals

A memory card system may include a flexible integrated circuit device package, an upper flexible case, a lower flexible case, a wiring structure, an anisotropic conductive film, etc. The flexible integrated circuit device package may include a material capable of being bent or folded and a flexible integrated circuit device having a connection pad for an electrical connection. The upper flexible case may include a material capable of being bent or folded and may cover the integrated circuit device package. The lower flexible case may include a material capable of being bent or folded and the flexible integrated circuit device package may be fixed to the lower flexible case. The wiring structure may include a material capable of being bent or folded, and also may include a connection wiring disposed on an inner surface of the upper flexible case for electrically connecting the flexible integrated circuit device package with an external device, a connection pin disposed on an outer surface of the upper flexible case, and a via wiring passing through the upper flexible case. The anisotropic conductive film may be disposed between the flexible integrated circuit device package and the upper flexible case for electrically connecting the connection pad with the connection wiring.

Memory card systems comprising flexible integrated circuit element packages, and methods for manufacturing said memory card systems

An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.

Integrated circuit device packages and methods for manufacturing integrated circuit device packages

An electronic component may include an integrated circuit device package and a second substrate. The integrated circuit device package may include a first substrate being bent or spread, a heat transfer member disposed in the first substrate, an integrated circuit device being bent or spread, a first pad disposed on one face of the integrated circuit device, and an adhesion member disposed between the integrated circuit device and the first substrate. The second substrate may be bent or spread. The second substrate may include a second pad. The integrated circuit device package may be combined with the second substrate by a thermo compression bonding process in which the heat transfer member may transfer a heat to the second substrate through the first substrate and the first pad may make contact with the second pad.

Electronic components

A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps

A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.

Nonvolatile memory device and fabricating method thereof

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.

Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices

A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.

SONOS memory device using an amorphous memory node material

A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

Semiconductor device having a gate contact structure capable of reducing interfacial resistance

Non-volatile memory devices including blocking and interface patterns between charge storage patterns and control electrodes and related methods

A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

Nonvolatile memory device having cell and peripheral regions and method of making the same

A printed circuit board having a built-in antenna may include a first unit substrate, in which a ground and a first radiator are formed; a second unit substrate, which is stacked over the first unit substrate, and in which a second radiator having a frequency band different from a frequency band of the first radiator is formed; a pair of striplines, formed in the first unit substrate and connected with the ground; a first via, which connects the first radiator with the second radiator; a pair of second vias, each of which has one end connected with the pair of strip lines respectively; and a connection pattern, which connects the other ends of the pair of second vias to each other. The printed circuit board having a built-in antenna can utilize multiple frequency bands, and can be implemented in a compact size, to be applicable in compact communication devices.

Printed circuit board having built-in antenna

A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

Method of operating a SONOS memory device

Growing community of inventors

Yongin-si, South Korea

Ju-Hyung Kim