Samsung Electronics Co., Ltd.

Ju-Hyung Hong

Hyun-Wook Lim

Il-Won Seo

Kwang-Seok Im

An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.

ECC control circuits, multi-channel memory systems including the same, and related methods of operation

A read circuit of a disk drive system that adaptively reduces signal-dependent noise including a sequence detector, a signal-dependent adaptive engine and a signal-dependent post-processor. The sequence detector recovers a data sequence from equalized data. The signal-dependent adaptive engine generates signal-dependent coefficients, a mean value and a standard deviation of a signal-dependent error. The signal-dependent post-processor corrects the signal-dependent error.

Growing community of inventors

Gyeonnggi-do, South Korea

Ju-Hyung Hong