Samsung Electronics Co., Ltd.

Skhynix Inc.

Hyundai Motor Company

Kia Motors Corporation

Samsung Electro-mechanics Co., Ltd.

Hyundai Mobis Co., Ltd.

Daewon Precision Industrial Co., Ltd

Rznomics Inc.

Ju Hyun Kim

Jin Yeong Kim

Do Hun Kim

Hyunseok Choi

Beom Seok Kim

Jae Wan Yeon

Sangah Gam

Hyun Seok Choi

Hong-Seok Lee

Seunghyun Lee

Joungeun Yoo

Yun Sup Ann

Tsuyoshi Ohyama

Kwang Sun Lee

Chang-Kun Lee

Hoon Song

Dong Woo Kim

Kitae Park

Jung Joo Lee

Taehyung Kim

Sang Ho Kim

Dae Young Chung

Bo Ki Hong

Eun Sung Lee

Won Sik Yoon

Dmitry Androsov

Hyun Seok Moon

Ha Il Kwon

Changki Kim

Kwang Hee Kim

Bang Won Oh

Jung Han Yu

Masashi Tsuji

Hyun-Seok Choi

Sang Seok Lee

Bong Ku Kim

Hee Joon Lee

Yong Seok Oh

Gi Bum Kim

Jin Pyo Kim

Keun Bong Ham

Hee Chan Shin

Young Ho Choi

Woong Sik Shin

Young Bok Sung

Jae Sun Han

Dong Il Lee

Woo Young Yang

Sunghyun Han

Hwa Sung Rhee

Seong Wook Lee

Da Eun Lee

Su Jin Park

Yun Suk Oh

Ha Yeong Son

Zhan Zhan

Sung Dug Kim

Jin Sook Jeong

Sang Young Han

Kee Bum Shin

Jong Soon Park

Chang Myung Song

Young Wook Woo

Jae Ryung Yoo

Woo Jae Jin

Jung Kwuen An

Sung Gun Kang

Jong Yang Park

Ki Wan Park

An operation method includes buffering data chunks to be programmed in the multi-level cells in a write buffer; backing up at least one backup data chunk of the data chunks to a backup memory; determining a program sequence of the data chunks, the program sequence for programming a non-backup data chunk among the data chunks to the multi-level cells through a second step program operation of the multi-step program operation; and controlling the memory device to program the data chunks in the multi-level cells, based on the program sequence, by performing first and second step program operations of the multi-step program operation in a first page of the multi-level cells, the second step program operation performed in the first page later than another first step program operation performed in a second page subsequent to the first page.

Controller and operation method thereof

An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Memory controller for scheduling commands based on response for receiving write command, storage device including the memory controller, and operating method of the memory controller and the storage device

A quantum dot device including an anode and a cathode, a light emitting layer disposed between the anode and the cathode, the light emitting layer comprising quantum dots, a first hole auxiliary layer disposed on the anode, the first hole auxiliary layer including poly(3,4-ethylenedioxythiophene)-polystyrenesulfonate or a derivative thereof (PEDOT:PSS), a second hole auxiliary layer disposed on the first hole auxiliary layer and including a hole transport material different from the PEDOT:PSS, wherein the light emitting layer is disposed on the second hole auxiliary layer, wherein the first hole auxiliary layer has a first surface facing the anode and a second surface facing the second hole auxiliary layer, and the second surface includes a surface modification region including a surface modification material having a carboxylic acid group, a phosphonic acid group, a sulfonic acid group, or a salt thereof. An electronic device that includes the quantum dot device.

Quantum dot device and electronic device

A memory system includes a memory device including a first memory block used for power-loss data protection and a controller coupled to the memory device. The controller includes a hardware layer and a firmware layer. The hardware layer checks whether at least one write data entry belongs to a programmable range in the memory device after power loss occurs, determines whether a logical address associated with the at least one write data entry is repeated, and programs the at least one write data entry in the first memory block.

Apparatus and method for power-loss data protection in a system

A camera system of a mobile device includes: a sensor module disposed in a first body connected to a rotation member of the mobile device; and a lens module disposed in a second body connected to the rotation member. When the first body and the second body are rotated with respect to the rotation member to overlap each other, optical axes of the sensor module and the lens module correspond to each other and are operated as a common camera system, and the common camera system provides a first photographing mode and a second photographing mode with different viewing angles based on two focuses generated by a first geometry phase lens included in the lens module.

Camera system of mobile device including geometry phase lens

The present technology relates to an electronic device. According to the present technology, a storage device that manages map data using a volatile memory device having a limited capacity may include a nonvolatile memory device, a memory controller, and the volatile memory device which includes a map chunk buffer, a map chunk status table, a journal buffer, and a meta slice buffer.

Storage device and method for updating meta slice including map chunks stored in nonvolatile memory device according to journal entries

A controller for controlling a memory device is provided to include: a request receiver configured to receive a request including a logical address from a host; a dependency checker configured to acquire the request from the request receiver and check a dependency of the request; a map manager configured to generate a command including a physical address mapped to the logical address of the request in response to a result of checking that the request has no dependency on the prior incomplete request; and a command submitter configured to provide the memory device with the command generated by the map manager, wherein the request receiver, the dependency checker, the map manager and the command submitter are structured to configure a data pipeline such that operations of the request receiver, the dependency checker, the map manager, and the command submitter deliver are performed in series.

Controller for performing data input/output operation and memory management operation at the same time and operation method thereof

A water electrolysis system includes a water electrolytic stack, a water reservoir connected to the water electrolytic stack to supply water to the water electrolytic stack, a water circulation pump supplying the water in the water reservoir to the electrolytic stack; and a control unit configured to, during an operation stoppage of the electrolysis system, control the driving of the water circulation pump to convert the water in the electrolytic stack from an acidic condition to a neutral condition and to regulate a unit cell voltage of the electrolytic stack to a voltage such that an electrolysis reaction does not occur and a chemical state of an anode catalyst is stably maintained.

Water electrolysis system

A memory system includes: a memory device including a plurality of memory dies including the plurality of planes; and a controller configured to store data in a plurality of stripes each including physical pages of different planes and a plurality of unit regions, the controller comprising: a processor configured to queue write commands in a write queue, and select, among the plurality of stripes, a stripe in which data chunks corresponding to the write commands are to be stored; and a striping engine configured to receive queued orders of the write commands, and output, by referring to a lookup table, addresses of unit regions, in which the data chunks are to be arranged, to the processor, wherein the processor in configured to control the memory device to store the data chunks in the unit regions corresponding to the outputted addresses of the selected stripe.

Memory system and operation method thereof

A memory system includes: a controller including first and second cores; a plurality of channels connected to the controller; a plurality of first memory devices each including first memory blocks allocated to the first core, each of the plurality of channels being coupled to at least one first memory device; and a plurality of second memory devices each including second memory blocks allocated to the second core, each of the plurality of channels being coupled to at least one second memory device, wherein the controller further includes: a global wear leveling manager configured to perform a global wear leveling operation by swapping a first memory block and a second memory block, which are connected to the same channel among the first memory blocks and the second memory blocks, between the first and second cores on the basis of wear levels of the first memory blocks and the second memory blocks.

Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system may configure a plurality of map cache pools for caching map data of different types, respectively, within a map cache in which the map data is cached, configure a timer in a first map cache pool among the plurality of map cache pools, and write map data cached in the first map cache pool in the memory device based on the timer.

Memory system, memory controller, and method of operating memory system

Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may store target data to be programmed in a memory device in a first memory, selectively store the target data in a second memory, program the target data stored in the first memory into the memory device, and reprogram the target data stored in the first memory or the second memory into the memory device when the programming of the target data stored in the first memory into the memory device fails. The buffer circuit may input the target data input from the memory controller into the second memory or discard the target data.

Memory system and operating method thereof

Growing community of inventors

Gyeonggi-do, South Korea

Ju Hyun Kim