Hyundai Mobis Co., Ltd.

Hyundai Autron Company Ltd.

Samsung Electronics Co., Ltd.

Iucf-hyu

Ju Hwan Lee

In Gun Kim

Min Jae Kim

Hyuk Woo

Young Joon Kim

Young Jae Park

Sin-Ae Kim

Tae Yang Kim

Min Gi Kang

Jeong Mok Ha

Hyo Won Sin

Tae Young Park

Han Sin Cho

Tae Yeop Kim

Sin A Kim

Tae Youp Kim

Hyun Seok Hong

Seong-hwan Yun

Seon Hyeong Jo

Seong Hwan Yun

Seon-hyeong Jo

A power semiconductor device includes a plurality of gate electrodes configured to be recessed from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, the second surface being opposite to the first surface, an emitter region configured to make contact with a trench and the first surface, being provided between respective ones of the plurality of gate electrodes, and including impurities of a first conductive type, a collector region configured to make contact with the second surface, and including second impurities of a second conductive type opposite to the first conductive type, a floating region extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and including the second impurities, and a trench emitter region interposed between the plurality of gate electrodes in the trench.

Power semiconductor device, power semiconductor chip including the same, and method for manufacturing the same

A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Power semiconductor device and method of fabricating the same

A power semiconductor device includes a semiconductor layer, first trenches recessed into the semiconductor layer from a surface of the semiconductor layer, a drift region, having a first conductivity type, disposed in the semiconductor layer to extend from a lower side the first trenches to between the first trenches such that a vertical charge transport path is provided, a well region disposed in the semiconductor layer on the drift region between the first trenches and having a second conductivity type, an emitter region disposed on the well region and having the first conductivity type, a floating electrode layer disposed in each of the first trenches, a second trench extending through the well region to be in contact with the drift region, and a gate electrode layer disposed in the second trench.

Power semiconductor device and power semiconductor chip

A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer.

Provided is a semiconductor device. The device comprises an epitaxial layer that constitutes a part of an active cell region and is doped with impurities of a first conductivity type at a first concentration; a field stop region that is located below the epitaxial layer and doped with impurities of a second conductivity type at a second concentration which are then activated; and a collector region that is located below the field stop regionand is doped with impurities of a second conductivity type. The field stop region is formed by repeatedly alternately arranging regions in which the activation of the impurities of the first conductivity type is relatively strong and regions in which the activation of the impurities of the first conductivity type is relatively weak.

The power semiconductor device includes: a first trench gate and a second trench gate in a stripe shape extending in one direction in parallel and spaced apart from each other in a substrate; a third trench gate in a ladder shape extending in a direction different from the one direction between the first trench gate and the second trench gate in the substrate; a first conductive type body area each disposed between the first trench gate, the second trench gate and the third trench gate, respectively, in the substrate; a pair of first conductive type floating first areas surrounding each of bottom surfaces and at least one side of the first trench gate and the second trench gate in the substrate; and a first conductive type floating second area surrounding a bottom surface of the third trench gate in the substrate.

Power semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device comprising a substrate including an active region and an edge region and containing a semiconductor doped with impurities having a first conductivity type; an insulating film disposed on the edge region of the substrate; a field plate pattern disposed on the insulating film; and at least one first doped region having a second conductivity type buried in the edge region of the substrate and extending in a direction having a vector component parallel to an upper surface of the substrate.

Power semiconductor device

Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.

Provided is a power semiconductor device comprising a pair of gate electrodes respectively disposed in a first trench and a second trench spaced apart from each other in a substrate; a body region having a first conductivity type disposed between the first trench and the second trench; a pair of floating regions having a first conductivity type spaced apart from each other and surrounding a bottom surface and at least one side surface of the first trench and the second trench, respectively; and a drift region having a second conductivity type which extends from below the pair of floating regions through a region between the pair of floating regions to the body region, wherein, in the drift region, the doping concentration of a second conductivity type between the pair of floating regions is higher than the doping concentration of a second conductivity type below the pair of floating regions.

A device and method for controlling the charging of a portable terminal is provided. The device includes an external power supply interface unit for supplying an external power, a battery interface unit to which a main battery and a sub battery are connected, and a charging controller for controlling a charge of the main battery or a simultaneous charge of the main battery and the sub battery.

Method and apparatus for controlling battery charging of portable device

A method of operating a Real Time Clock (RTC) in a terminal is provided. The method includes detecting a clock signal transmitted to an RTC block when the main power supply is switched off, and supplying a power to the RTC block for its operation by charging and discharging the power periodically supplied from the backup battery according to the detected clock signal. A DC/DC converter connected to a backup battery is periodically switched on and off, and a capacitor is charged and discharged using the power of the backup battery, thereby avoiding supplying power from a backup battery continuously to an RTC block. Therefore, power consumption is reduced and a duration of time for maintaining RTC data is extended.

Growing community of inventors

Suwon-si, South Korea

Ju Hwan Lee