Amkor Technology, Inc.

Ju-Hoon Yoon

Dae-Byung Kang

Vincent DiCaprio

Markus K Liebhard

In-Bae Park

Chang-Bok Lee

Sung-Jin Yang

Woo-Hyun Kong

A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips and circuit pattern units, is/are pre-tested and discriminated in terms of the quality and/or grade of each individual chip unit and/or circuit pattern unit contained therein. The test results are marked on the lower surface of each chip unit and/or on each pattern unit. The substrate is laminated to the wafer to form a laminated assembly prior to performing the packaging process, which typically includes a wire bonding step, an encapsulation step and a solder ball welding step. A plurality of connected package units are thereby formed in the laminated substrate-wafer assembly. The package units are then singulated from each other and the laminated assembly by a cutting process. Using the pre-testing results, the method eliminates wasteful packaging of defective chips. The quality and/or grade of packaged units are marked on the chips in accordance with the pre-testing data, thereby enabling defective packages to be distinguished from good packages without need for post-singulation testing. The method permits using only good circuit pattern units, thereby preventing expensive chip units from being packaged with defective pattern units. In addition, the method permits both a package pick-and-place step and a package marking step to be combined into a single operation using a single device.

Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques

A circuit pattern tape for the wafer-scale production of chip size semiconductor packages is adapted to be laminated onto a semiconductor wafer and includes a flexible insulating layer, a plurality of identical circuit pattern units arrayed thereon, and a solder mask covering the circuit patterns. Each circuit pattern unit includes a central opening, a plurality of bond fingers arranged on opposite sides of the opening and electrically connected through the opening to associated die pads on an underlying semiconductor chip in the wafer, a plurality of solder ball lands, each having a solder ball attached thereto, and a plurality of conductive traces electrically connecting respective ones of the bond fingers and the solder ball lands to each other. The bond fingers and central opening are arranged so that they do not intersect singulation lines defining the coincident edges of the corresponding individual circuit pattern units and chips after they are cut from the wafer-tape assembly, thereby eliminating chipping of the wafer. The circuit pattern units may include a dummy pattern that is made of the same conductive metal as the solder ball lands, the conductive traces, and the bond fingers, and which is arranged on the circuit pattern to achieve a uniform distribution of the conductive metal thereon and thereby minimize voids between the tape and the wafer and bowing in the dissimilar materials of the tape due to a change in its temperature.

Circuit pattern tape for wafer-scale production of chip size semiconductor packages

A method for laminating a circuit pattern tape over a wafer, involving the steps of preparing a circuit pattern tape formed with an adhesive layer, along with a wafer, detecting at least one reference position of the prepared circuit pattern tape and at least one reference position of the prepared wafer using visual detecting means, outputting results obtained at the detecting step in the form of visual images capable of allowing a comparison of the detection results, carrying out a reference position correction involving movements of the wafer in an X-axis and/or a Y-axis direction and/or by a desired angle, thereby allowing the reference position of the circuit pattern tape and the reference position of the wafer to correspond to each other, and laminating the circuit pattern tape over the wafer when the reference positions correspond to each other.

Method for laminating circuit pattern tape on semiconductor wafer

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Seoul, South Korea

Ju-Hoon Yoon