Samsung Electronics Co., Ltd.

Ju-Ho Jeon

Jung-Hwan Choi

Hun-Dae Choi

Chang-Kyo Lee

Han-gi Jung

Yoo-Chang Sung

Jin-Seok Heo

Wang-Soo Kim

Ki-Duk Park

Jin-Sung Youn

Jin-Hee Park

Hyuck-Joon Kwon

A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Memory modules, memory systems and methods of operating memory modules

An electrostatic protection circuit with variable Schmitt trigger characteristics is provided. The electrostatic protection circuit uses a Schmitt trigger circuit to protect an integrated circuit against an overvoltage. The Schmitt trigger circuit includes first and second branches bridged between a power supply rail and a ground rail. The Schmitt trigger circuit operates with a narrow hysteresis width when the second branch is connected in parallel to the first branch and with a wide hysteresis width when the second branch is not connected in parallel to the first branch. The electrostatic protection circuit discharges an overvoltage of the power supply rail using a narrow hysteresis width when a weak overvoltage is applied to the power supply rail, and discharges an overvoltage of the power supply rail using a wide hysteresis width when a strong overvoltage is applied to the power supply rail.

Electrostatic discharge protection circuit having variable schmitt trigger characteristics

A memory device may be configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device may include control circuitry configured to, extract a common mode of the differential data strobe signal to generate a common mode signal, generate an internal data signal based on the external data signal and the common mode signal, and generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.

Memory device including common mode extractor

A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

Memory device and method of operating the same for latency control

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Bucheon-si, South Korea

Ju-Ho Jeon