Samsung Electronics Co., Ltd.

Ju-hee Park

Yoon-Dong Park

Jae-woong Hyun

Kyoung-Lae Cho

Seung-hoon Lee

Seung-Hwan Song

Sung-Jae Byun

Sang-Moo Choi

Sang-jin Park

Jun-Jin Kong

In-Jun Hwang

Sang-min Shin

Young-hoon Jeong

Kwang-soo Seol

Jae-min Lee

Kee-Won Kwon

Jung-hun Sung

Il-do Kim

Won-kyu Hwang

Keum-seok Lee

Sung-chung Park

Young-moon Kim

A photographing method and apparatus are provided. In the method, an image signal of an object region is detected from an input image signal, a shadow region is detected from the object region image signal, and an image signal obtained by superimposing the shadow region on the object region image signal is displayed. When removal of a shadow is requested after the input image signal is captured, the photographing method corrects a brightness level of the shadow region. The photographing apparatus includes an object region detecting unit configured to detect an image signal of an object region from an image signal; a shadow region detecting unit configured to detect a shadow region from the object region image signal, and an image signal superimposing unit configured to output an image signal detected by superimposing the shadow region detected by the shadow region detecting unit onto the object region image signal detected by the object region detecting unit.

Photographing method and apparatus providing correction of object shadows, and a recording medium storing a program for executing the method

A method and apparatus are provided for eliminating image noise to remove spatial-temporal noise and improve visibility. The method includes extracting a spatial-temporal noise level of neighbor pixels around a current pixel, filtering noise of the current pixel by applying a weight to spatial-temporal pixels around the current pixel based on the extracted spatial-temporal noise level, and applying a weight to the noise-filtered pixel and a boosted-up pixel based on an edge intensity and summing the weight-applied pixels. The spatial-temporal noise level is extracted based on spatial-temporal information of neighbor pixels around a current pixel in a current frame and spatial-temporal information of neighbor pixels around a current pixel in a previous frame.

Method of and apparatus for eliminating image noise

Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

Non-volatile memory device including block state confirmation cell and method of operating the same

Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ibit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.

Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups

A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

Methods of programming non-volatile memory cells

A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

Semiconductor memory device including recessed control gate electrode

Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations

A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.

Method of operating a semiconductor memory device having a recessed control gate electrode

A non-volatile memory device may include at least one string, at least one bit line corresponding to the at least one string, and/or a sensing transistor. The at least one string may include a plurality of memory cell transistors connected in series. The sensing transistor may include a gate configured to sense a voltage of the corresponding bit line. A threshold voltage of the sensing transistor may be higher than a voltage obtained by subtracting a given voltage from a voltage applied to read the corresponding bit line connected to a memory cell transistor to be read of the plurality of memory cell transistors.

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Guri-si, South Korea

Ju-hee Park