Winbond Electronics Corporation

Windbond Electronics Corp.

Ju-Chieh Cheng

Lih-Wei Lin

Lung-Chi Cheng

Tsung-Huan Tsai

I-Hsien Tseng

Ying-Shan Kuo

Chia-Hung Lin

Jun-Yao Huang

Ping-Kun Wang

Ngatik Cheung

Yu-An Chen

Yu-Cheng Chuang

Po-Wei Huang

Shan-Hsuan Tsai

A memory device and an enhance programming method thereof are provided. The enhance programming method includes: performing program and verifying operations on a plurality of memory cell groups of a memory division, where each of the memory cell group corresponds to at least one byte; calculating a programming time for completing program operation of each of the memory cell groups; setting an indication flag when the programming time is larger than a preset threshold value; and, when the indication flag is in a setting state, increasing at least one of a plurality of program operation parameters, and performing an enhancement programming operation on the memory cell groups of the memory division.

Memory device and enhance programming method thereof

A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

Forming operation of resistive memory device

An erasing method of a memory device includes the following steps. It is determined whether a memory passes the first erasing verification operation according to the first erasing verification threshold. When the memory does not pass the first erasing verification operation, an erasing operation is performed on the memory. When the memory passes the first erasing verification operation, a flag is generated and it is determined whether the memory passes a second erasing verification operation according to the second erasing verification threshold. When the memory does not pass the second erasing verification operation, the erasing operation is performed on the memory. When the memory passes the second erasing verification operation, an over-erase correction is performed on the memory. It is determined whether there is a flag indicating that all addresses pass the first erasing verification to determine whether the memory passes the first or second erasing verification operation.

Memory device and erasing method thereof

A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.

Method for erasing flash memory

A resistive memory storage apparatus including a memory cell, a selecting transistor and a memory controller is provided. The memory cell outputs a writing current during a writing pulse width period. The selecting transistor is coupled to the memory cell. The memory controller is coupled to the selecting transistor and the memory cell. The memory controller is configured to apply a control voltage that gradually changes to a predetermined voltage level to a control end of the selecting transistor during a resistance transition phase of the writing pulse width period and set the control voltage to the predetermined voltage level during a filament stabilization phase after the resistance transition phase, so as to limit the writing current to a predetermined current value. In addition, an operating method for a resistive memory storage apparatus is also provided.

Resistive memory storage apparatus and operating method thereof

A data writing method is provided. According to the present application, the data writing method includes steps of receiving an expected data, performing a plurality of readings on a target storage unit to obtain a plurality of read data; determining whether the plurality of read data are the same as the expected data respectively to generate a plurality of comparison results; and performing a writing operation procedure on the target storage unit according to the plurality of comparison results and the expected data.

Memory device and data writing method

A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method for write-in voltage includes: selecting an under test memory cell array in a resistive memory; performing N reset operations on a plurality of memory cells of the under test memory cell array according to a reset voltage, and performing N set operations on the memory cells of the under test memory cell array according to a set voltage, wherein n is an integer greater than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.

Resistive memory apparatus and adjusting method for write-in voltage thereof

An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.

Operating method of resistive memory storage apparatus

A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.

Memory-testing methods for testing memory having error-correcting code

A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.

Resistive memory storage apparatus and writing method thereof including disturbance voltage

A resistive memory and a data writing method for a resistive memory cell thereof are provided. The method includes: receiving and decoding a column address signal for generating a decoded result, and providing a word line voltage to a word line of the resistive memory cell; providing a constant current to one of a bit line and a source line of the resistive memory cell, and coupling a reference ground voltage to another one of the bit line and the source line of the resistive memory cell.

Resistive memory and data writing method for memory cell thereof

A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.

Devices and methods for programming a resistive random-access memory

A measurement system including a testing machine and a resistive memory is provided. The resistive memory includes a first storage cell. The first storage cell includes a transistor and a variable resistor. During a specific period, the testing machine provides a write voltage to change the state of the variable resistor. During a maintaining period, the testing machine maintains the level of the write voltage and measures the current passing through the variable resistor. When the current passing through the variable resistor does not arrive at a pre-determined value, the testing machine increases the level of the write voltage. Furthermore, a resistive memory utilizing the testing machine is also provided.

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Taichung, Taiwan

Ju-Chieh Cheng