Lg Philips Lcd Co., Inc.

Lg Display Co., Ltd.

Ju Cheon Yeo

Yong Min Ha

Sang Young Yoon

Jin Sang Kim

Jae Deok Park

Soon Kwang Hong

Byeong Koo Kim

A liquid crystal display driving method that is adapted to enhance a quality of picture to be displayed on a liquid crystal panel and prevents a distortion of picture. The liquid crystal display driving method drives a liquid crystal display device including a plurality of demultiplexers connected between a data driving circuit and data lines on a liquid crystal panel, and classifying color data signals to be applied to the respective demultiplexers data driver by colors and allowing the color data signals having a same color to be continuously supplied to the data lines by the demultiplexers prior to a different color signal having a different color.

Method of driving liquid crystal display

A liquid crystal display and a method for fabricating the same include a first substrate having an active layer with source/drain regions formed therein, a gate line and a data line extending in directions perpendicular to each other formed thereon, a dummy gate insulating film and a dummy gate electrode both formed on the first substrate in fixed patterns isolated from the gate line, an interlayer insulating film on the first substrate inclusive of the dummy gate electrode with a step, a drain electrode formed on the interlayer insulating film to overlap on upper regions of the dummy gate electrode so as to be in contact with the drain region and have a step to the data line, the data line formed on the interlayer insulating having a step to the drain electrode, a passivation film formed on the interlayer insulating film inclusive of the dummy gate electrode and the data line, a contact hole formed to expose the drain electrode overlapped with the dummy gate electrode, and a pixel electrode overlapping upper edges of the data line and in contact with the drain electrode through the contact hole, thereby reducing a vertical crosstalk while a large aperture is achieved, to improve the picture quality.

Liquid crystal display and method for fabricating the same

A data line driving method for a liquid crystal display device that does not require a separate pre-charge circuit and is capable of reducing pre-charge time operates by charging data lines to a desired level in response to a control signal for sampling the data lines. In one aspect, such a data line driving method includes the steps of generating a control signal; mutually short-circuiting the data lines in response to the control signal; pre-charging data lines to a desired level; mutually open-circuiting the data lines in response to the control signal; and sequentially applying video signals to the data lines in response to the control signal. A liquid crystal display device operable according to such a method includes data driving means for generating a pre-charging signal having a desired level; means for generating a control signal; and switching means for commonly applying the pre-charging signal to the data lines in response to the control signal, to pre-charge the data lines.

Method and system of driving data lines and liquid crystal display device using the same

TFT-LCD having dummy gate electrode and dummy gate insulator

A shift register for driving a pixel row in a liquid crystal display device. In the shift register, a plurality of stages are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, connected to row lines, and connected, in cascade, with respect to a scanning signal, for charging and discharging the row lines. In each stage of the shift register, an output circuit is provided with a pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the raw line and a first control electrode, and a pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line and a second control electrode. An input circuit responds to the scanning signal to generate a first control signal to be applied to the first control electrode, and responds to a second clock signal having a delayed phase in comparison to the first clock signal to generate a second control signal to be applied to the second control electrode.

Shift register

A shift register circuit is provided that is adaptive for reducing a swing width of a clock voltage. In the shift register, a plurality of stages, one for each scanning line, generate first driving signals in response to first and second clock signals. A level shifter is connected between each the stages and its respective scanning line to receive the first driving signal, to thereby apply a second driving signal having a larger swing width than the first driving signal to the scanning line.

Shift register circuit

In a shift register for driving a pixel row in a liquid crystal display device a plurality of stages are connected: to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator; to row lines; and in cascade, with respect to a scanning signal, for charging and discharging the row lines. Each stage of the shift register has a pull-up transistor, a pull-down transistor, and first to fourth transistors. The pull-up transistor has a control electrode and a conduction path connected between the first clock signal line and the output terminal. The pull-down transistor has a control electrode and a conduction path connected between the low level voltage line and the output terminal. The first and second transistors have conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each has a control electrode connected commonly to the second clock signal line. The first and second transistors allow a voltage to be charged on the control electrode of the pull-up transistor. The third and fourth transistors have conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor, and each has a control electrode connected commonly to the third clock signal line. The third and fourth transistors allow a voltage to be charged on the control electrode of the pull-down transistor.

A shift register for driving a pixel array is adapted to prevent a defect due to a short of a capacitor. In each stage of the shift register, an output circuit is provided with a pull-up transistor having a first input electrode for receiving a first clock signal, a first output electrode connected to a row line and a first control electrode, and a pull-down transistor having a second input electrode connected to a low-level voltage source, a second output electrode connected to the row line and a second control electrode. An input circuit generates a first control signal to be applied to the first control electrode and a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal. A first capacitor is connected between the input circuit and the row line, a second capacitor is connected between the second control electrode and the low-level voltage source, and a third capacitor is connected between the first control electrode and the low-level voltage source. At least one of the first to third capacitors has associated therewith a second capacitor connected in series thereto.

A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an output circuit responds to a first control signal to apply any one of first and second clock signals to a row line of a liquid crystal cell array and thus to charge the low line of the liquid crystal cell array, and responds to a second control signal to discharge a voltage at the row line. An output circuit responds to a clock signal different from any one of the start pulse and an output signal of the previous stage to generate the first control signal, and responds to a clock signal different from the first control signal to generate the second control signal.

Growing community of inventors

Anyang-shi, South Korea

Ju Cheon Yeo