Texas Instruments Corporation

Other

Ju-Ai Ruan

Tae S Kim

Changming Jin

Sopa Chevacharoenkul

Anand J Reddy

Gregory Boyd Shinn

Phillip D Matz

Sameer Kumar Ajmera

Joe G Tran

Kenneth Joseph Newton

Basab Chatterjee

Shawn T Walsh

James B Friedmann

Wayne A Bather

Michelle L Hartsell

Troy A Yocum

Jaideep Mavoori

Mercer Brugler

Sarah Hartwig

Somit Joshi

Satyavolu Papa Rao

Glenn J Tessmer

John E Campbell

Ching-Te Lin

Michael J McGranaghan

Janice D Makos

Arun Sivasothy

A novel method of modulating the motion or displacement of function units in MEMS (micro-electro-mechanical-system) devices (or MEMS motion transducers) is described. This method generates small vertical displacement of one MEMS component (activation component) in the device and effectively translates that displacement into the displacement of another MEMS component (function unit) in the same device in an in-plan direction that is perpendicular to the direction of the vertical displacement of activation component. The activation component has a large surface area of electrostatic interaction with its interacting electrode, capable of generating large activation force at small voltages. Therefore this method makes it effective to modulate the motion or displacement of the function unit of MEMS motion transducers in an in-plan direction at low voltages. Specific designs of MEMS motion transducers employing this method are disclosed.

Micro-electro-mechanical motion transducer

A spatial light modulator suitable for flat panel displays and methods of making the modulators are disclosed. The light modulator comprises a light separator, integrated circuits (IC), light switches (concurrently called light shutters), and optional color filters. The light separator is used to direct light uniformly illuminated on the incident surface (entrance surface) into individual pixels, and condenses the light within each pixel to a small fraction of pixel space on the viewing surface. ICs and light shutters are used to control color and light intensity at individual pixels. Several novel designs of the light modulator and light shutters are disclosed. Methods of building self-aligned structures for placing micro-spherical ball spacers for attaching protective screens to the light modulator is also disclosed.

Transmission and reflection dual operational mode light processing device

A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

Semiconductor device manufactured by reducing hillock formation in metal interconnects

One aspect of the invention provides a method of forming a semiconductor device (). One aspect includes forming transistors () on a semiconductor substrate (), forming a first interlevel dielectric layer () over the transistors (), and forming metal interconnects () within the first interlevel dielectric layer (). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer () over the metal interconnects () and the first interlevel dielectric layer () within a deposition tool. An adhesion layer () is formed on the SiCN layer (), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer () is formed over the adhesion layer ().

Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer

A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Reduction of punch-thru defects in damascene processing

The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again. According to one exemplary aspect, the first and second substrates are exposed to a first temperature in the first process chamber for approximately half the time the first and second substrates are exposed to a higher second temperature in the second process chamber while maintaining throughput of substrates.

Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

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Plano, TX, United States of America

Ju-Ai Ruan