Intel Corporation

Jr-Shian Tsai

Tsung-Yuan Charles Tai

Ren Wang

Mesut A Ergin

Alexander W Min

Andrew J Herdrich

Ravi L Sahita

Rajesh M Sankaran

Christian Maciocco

Edwin Verplanke

Prakash N Iyer

Gilbert A Neiger

Emily H Qi

Barry E Huntley

Bruce L Fleming

Yipeng Wang

Iosif Gasparakis

Namakkal N Venkatesan

Jun Nakajima

David M Durham

Kapil Sood

Baiju V Patel

Jesse R Walker

Michael Lemay

Debra Bernstein

David Sonnier

Scott P Dubal

Vadim Sukhomlinov

Stephen R Van Doren

Stephen T Palermo

Sameh Gobriel

William G Burroughs

Hugh Wilkinson

Niall D McDonnell

Jesse C Brandeburg

Andrew Cunningham

Mingwei Zhang

Bruce Richardson

James T Clee

Narender R Vangati

Trevor Cooper

Jerry Pirog

Chih-Fan Hsin

Vedvyas Shanbhogue

Christopher J Hughes

Jason W Brandt

Michael E Kounavis

Karanvir S Grewal

Yen-Cheng Liu

Herbert H Hum

Wei Wang

Jong Soo Park

Anjali Singhai Jain

Zeshan A Chishti

Rajeev D Muralidhar

Bradley A Burres

Harinarayanan Seshadri

Nilesh K Jain

Aamer Jaleel

Adrian C Moga

Cunming Liang

Tsung-Yuan Charlie Tai

Josh Triplett

Kshitij Arun Doshi

Mohan J Kumar

Paul S Diefenbaugh

Patrick L Connor

Ravishankar Iyer

Arvind A Kumar

James P Kardach

Sara S Baghsorkhi

Eugene Gorbatov

Parthasarathy Sarangam

Sanjay Bakshi

Alexander Bachmutsky

Mingqiu Sun

Guan-Yu Lin

Ian M Steiner

Ashish V Choubal

Narayan Ranganathan

Andrew D Henroid

Jeffrey D Chamberlain

Brian J Skerry

Eric Dahlen

Brinda Ganesh

Thomas M Slaight

Mohammad R Haghighat

Somnath Paul

Nrupal R Jani

Ping Yu

Amin Firoozshahian

Eric K Mann

Changwen Liu

Sanjay Rungta

Hani Elgebaly

Ahmad A Samih

Rashmin N Patel

Carol Bell

Yeluri Raghuram

Jianghong Du

A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

Aperture access processors, methods, systems, and instructions

Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

Hardware offload circuitry

In some examples, for process-to-process communication, such as in function linking, a virtual channel can be provisioned to provide virtual machine to virtual machine communications. In response to a transmit request from a source virtual machine, the virtual channel can cause a data copy from a source buffer associated with the source virtual machine without decryption or encryption. The virtual channel provisions a key identifier for the copied data. The destination virtual machine can receive an indication data is available and can cause the data to be decrypted using a key accessed using the key identifier and source address of the copied data. In addition, the data can be encrypted using a second, different key for storage in a destination buffer associated with the destination virtual machine. In some examples, the key identifier and source address is managed by the virtual channel and is not visible to virtual machine or hypervisor.

Process-to-process secure data movement in network functions virtualization infrastructures

Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

Function as a service (FaaS) system enhancements

In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Generating, at least in part, and/or receiving, at least in part, at least one request

Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.

Encoded inline capabilities

Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Processor and method implementing a cacheline demote machine instruction

Technologies for monitoring network traffic include a computing device that monitors network traffic at a graphics processing unit (GPU) of the computing device. The computing device manages computing resources of the computing device based on results of the monitored network traffic. The computing resources may include one or more virtual machines to process network traffic that is to be monitored at the GPU of the computing device. Other embodiments are described and claimed.

Technologies for GPU assisted network traffic monitoring and analysis

Examples may include a method of compiling a declarative language program for a virtual switch. The method includes parsing the declarative language program, the program defining a plurality of match-action tables (MATs), translating the plurality of MATs into intermediate code, and parsing a core identifier (ID) assigned to each one of the plurality of MATs. When the core IDs of the plurality of MATs are the same, the method includes connecting intermediate code of the plurality of MATs using function calls, and translating the intermediate code of the plurality of MATs into machine code to be executed by a core identified by the core IDs.

Data plane semantics for software virtual switches

Technologies for managing a single-producer and single-consumer ring include a producer of a compute node that is configured to allocate data buffers, produce work, and indicate that work has been produced. The compute node is configured to insert reference information for each of the allocated data buffers into respective elements of the ring and store the produced work into the data buffers. The compute node includes a consumer configured to request the produced work from the ring. The compute node is further configured to dequeue the reference information from each of the elements of the ring that correspond to the portion of data buffers in which the produced work has been stored, and set each of the elements of the ring for which the reference information has been dequeued to an empty (i.e., NULL) value. Other embodiments are described herein.

Technologies for managing single-producer and single consumer rings

Technologies for monitoring network traffic include a computing device that monitors network traffic at a graphics processing unit (GPU) of the computing device. The computing device manages computing resources of the computing device based on results of the monitored network traffic. The computing resources may include one or more virtual machines to process network traffic that is to be monitored at the GPU the computing device. Other embodiments are described and claimed.

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

Growing community of inventors

Portland, OR, United States of America

Jr-Shian Tsai