Koninklijke Philips Corporation N.V.

Jozef Louis Van Meerbergen

Lennart Yseboodt

Jeroen Anton Johan Leijten

Anteneh Alemu Abbo

Josephus Antonius Huisken

Martinus Theodorus Bennebroek

Johannus Theodorus Matheus Hubertus Dielissen

Adwin Hugo Timmer

Octavio Alejandro Santana

Fran&ccedil;oise Jeannette Harmsze

A sensor device includes at least one autonomous streaming module. Predetermined internal events of the autonomous streaming module or predetermined external events from streaming data at an interface to a smart shell of the autonomous streaming module are detected. An operational mode of a component or subsystem within the smart shell of the autonomous streaming module is controlled in response to the detection.

Wireless sensor node architecture with autonomous streaming

A turbo decoder system () for decoding turbo coded bits, is provided with a system input () and a plurality of turbo decoders (--n) each having a turbo decoder input (--n). The plurality of turbo decoders (--n) is arranged in parallel, and the system () is further provided with an allocating device () coupled between the system input () and the turbo decoder inputs (--n) for dynamically allocating the turbo coded bits to one of the turbo decoders (-n).

Turbo decoder system comprising parallel decoders

A data processor has a cache memory with an associative memory for storing at least a first and second groups of associations between a respective main memory addresses and cache memory locations. At least one cache memory location is dynamically assignable to different ones of the groups for use in associations of the assigned group. When an instruction indicates a main memory address a group is selected group for finding the cache memory location associated with the main memory address. In an embodiment, the processor accesses streams of addresses from iteratively computed main memory addresses. Each stream has its own group of associations of addresses from the stream with cache memory locations assigned to that group. The remaining cache memory locations are accessed with set associative mapping. Thus, cache memory locations can be assigned to different streams on an &ldquo;as needed&rdquo; basis and the remaining cache memory locations can be used for non-stream addresses.

Data processor utilizing set-associative cache memory for stream and non-stream memory addresses

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Zoersel, Belgium

Jozef Louis Van Meerbergen