Koninklijke Philips Corporation N.v.

Nxp B.v.

St-ericsson Sa

Callahan Cellular LLC

Jozef Laurentius Wilhelmus Kessels

Adrianus Marinus Gerardus Peeters

Ivan Andrejic

Wolfgang Eber

Dominik Josef Berger

Ralf Malzahn

Patrick Willem Hubert Heuts

Volker Timm

Paul Wielage

Torsten Kramer

Suk Jin Kim

A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted.

Data processing circuit with multiplexed memory

A circuit is described comprising a first () and a second circuit module () and a synchronization module (). The first and the second module are mutually asynchronous, and are coupled by the synchronization module. The synchronization module () comprises: a transfer register () for storing data which is communicated between the two circuit modules, a control circuit () for controlling the register in response to a respective timing signal (St, St) from the first and the second circuit module, the control circuit comprising a control chain for generating a control signal (CR) for the transfer register (). The control chain includes at least: a repeater () for inducing changes in the value of the control signal, at least one edge sensitive element () for delaying a change in the signal value until a transition in a selected one of the timing signals is detected.

Circuit comprising mutually asynchronous circuit modules

Pipeline synchronization device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronization device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronization device comprises further a synchronizer adapted to synchronizing the change in a signalling output with the clock of the external device.

Pipeline synchronisation device

A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made. The timing circuit varies the position of the acceptance time points within the validity duration intervals, so that the position is delayed to make room for previously accepting an access request from another processor. The position is subsequently moved back toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit.

A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by traveling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.

Information exchange between locally synchronous circuits

A data carrier is disclosed. The data carrier includes a data processing unit and at least one contactless interface via which the data processing unit can be coupled to a read/write apparatus in order to exchange data signals and to take up electrical energy for the operation of the data processing unit; the data processing unit is constructed at least mainly while using at least substantially asynchronously operating logic components (asynchronous logic). The data carrier according to the invention, such as a chip card, makes optimum use of the energy applied thereto and is at the same time protected against the tapping of the signal processing steps to be executed therein.

Data carrier

An integrated circuit according to the invention comprises at least a first and a second circuit ( resp.) and a first and a second signal path ( and resp.) between the first and the second circuit. The first and the second signal path each comprise a selection element ( ) which has a first input ( ) coupled to the first circuit ( ), and a second input ( ). The selection element ( ) has an output (30 ) coupled to the second circuit ( ). The second input ( ) of the selection element ( ) of the second signal path ( ) is coupled to a memory element ( ). The output ( ) of the selection element ( ) of the first signal path ( ) is coupled to an input ( ) of the memory element ( ).

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Eindhoven, Netherlands

Jozef Laurentius Wilhelmus Kessels