U.S. Philips Corporation

Jozef L Van Meerbergen

Antoine Delaruelle

Franciscus J Van Wijk

Robert J Sluijter

Hendrikus J Veendrick

Josephus Antonius Huisken

Cornelis Niessen

Franciscus P Beenker

Adwin Hugo Timmer

Rudi J Stans

Luc L Matterne

Owen P McArdle

Paul E Lippens

Hendricus A Hilderink

Jeroen A Leijten

Fransiscus P Welten

Franciscus P Welten

Distributed digital signal processing is executed by a number of processing elements. Signal processing processes are scheduled for individual processing elements according to the data flow principle. To this end, the flow of signal samples is subdivided into data tokens, each of which has several samples. A process is started in a processing element in response to the detection of a data token presented so as to undergo the process. The detection is processed by a control unit which, in response thereto, allocates a communication connection between a first processing element producing the relevant data token and a second processing element which is to process the data items present in the data token. Scheduling is thus achieved by allocation of the communication connection. Furthermore, in order to avoid deadlock problems, restrictions are imposed as regards the execution sequence of processes.

Signal processing device

A data processor of modular architecture comprises a plurality of operation units, each serving to implement specific functionalities as required by the instruction set that determines the processor's operation. Register files for several ones among the operation units are merged. At least one of the register files is exclusively assigned to one of the operation units. At the expense of only a marginal increase, if any, of the number of instruction cycles, smaller register file areas in an IC embodiment, less register file control circuitry and simpler microcode words are obtained.

Data processor with operation units executing dyadic and monadic

A buffer memory device comprising memory locations for successively storing successive groups of data units, the successive groups being presented during successive phases, the data units in each group having different buffer periods which are recurrent for all groups. A modulo address generator generates, for each group of data units, a series of addresses for selected locations in a memory wherein the data units will be stored, there being logic address intervals between the successive addresses in the relevant series which correspond to the buffer periods of the respective data units. In every two successive series the memory addresses are shifted by one address interval unit with respect to each other. An efficient data occupation of the memory can thus be realized with simple addressing, since the write addresses during any phase can be used as the read addresses for already stored data units. The buffer device can be used as an interleaver or de interleaver for error correction in CD apparatus.

Data buffer for the duration of cyclically recurrent buffer periods

A modified Booth multiplier for multiplying an m-bit number X by an n-bit number Y comprises a Booth encoder for converter the number Y in groups of 3 bits which overlap by 1 bit into a series Y' of multiplication values whose number is equal to or substantially equal to half the number of bits of Y. There is also provided a multiplex circuit for forming partial products from the number X and said series Y' and a matrix configuration of full adders for adding the partial products in incremental positions. The design is such that the constituent components and the operation of the modified Booth multiplier can be tested by means of a very small number of test patterns which are generated in the Booth multiplier after application of a specific series of X,Y-values. Test patterns are generated for establishing static as well as dynamic errors in the combination formed by the Booth encoder and the multiplex circuit and also test patterns which are formed by specific partial products in order to establish static errors in the matrix configuration. In practice the modified Booth multiplier is usually constructed as a multiplier accumulator; in that case test patterns formed by partial products are also used for establishing static errors in the accumulator section.

Method of testing a modified booth multiplier, modified booth multiplier

A data-processing apparatus having a processor, a read-write memory, a data bus, a program counter, a program memory and an instruction register. There is also a feedback finite-state machine possessing a multibit-wide output whose bits are determined in at least two successive machine cycles. This output is connected to a comparator which has its other input connected to the instruction register. A certain equality condition can invalidate the current instruction so that the latter acts as a rapidly performable dummy (NOP) instruction and a program jump can be performed. In a further expansion another multibit-wide output of the finite-state machine can be coupled to the data bus via a decoding circuit.

Data-processing apparatus provided with a finite-state machine to

A logic circuit incorporating carry look-ahead in which efficiency can be achieved regarding the hardware for generating the sum signals and carry signals by a suitable choice of the adder gate, making use of the already present signal a.sub.1 .multidot.b.sub.i which is used for generating the carry look-ahead signal.

Logic full adder circuit

An integrated and programmable processor for word-wise digital signal processing. The processor has a multiplier element, an arithmetic and a logic unit, a data memory and a connection for a control memory which may be integrated on-chip. The elements are interconnected by means of a double bus on which addresses as well as data may be transported by means of suitable selectors. Consequently, a pipeline operation can take place within one instruction cycle.

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Eindhoven, Netherlands

Jozef L Van Meerbergen