Agere Systems Inc.

Lucent Technologies Inc.

Joze E Antol

John William Osenbach

Sailesh Mansinh Merchant

Taeho Kook

Daniel Patrick Chesire

Philip William Seitzer

Vance Dolvan Archer

Rafe Carl Mengel

Thomas B Gans

Kishor V Desai

Kurt George Steiner

Gustav Edward Derkits, Jr

David Gerald Coult

Brian Thomas Vaccaro

Nur Selamoglu

Franklin Roy Dietz

Ronald James Weachock

According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent damage to such dielectric material, bond pads are fabricated with support structures that shield the dielectric material from destructive forces during wire bonding. In one implementation, the support structure includes a passivation structure between the bond pad and the topmost metallization layer. In another implementation, the support structure includes metal features between the topmost metallization layer and the next-topmost metallization layer. In both cases, the region of the next-topmost metallization layer under the bond pad can have multiple metal lines corresponding to different signal routing paths. As such, restrictions on the use of the next-topmost metallization layer for routing purposes are reduced compared to prior-art bond-pad support structures that require the region of the next-topmost metallization layer under the bond pad to be a single metal structure.

Bond pad support structure for semiconductor device

It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 &#x3bc;m or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Integrated circuit package including wire bonds

Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.

Manufacture of devices including solder bumps

Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe regionfrom the wire bond regionand forming the bond padover active circuitry has several advantages. By separating the probe regionfrom the wire bond region, the wire bond regionis not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond padover active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

Reinforced bond pad for a semiconductor device

The specification describes an analytical technique for determining trace levels of copper in a background matrix of titanium by dissolving the titanium and the copper impurity in HF, then selectively depositing the copper on a clean silicon surface. The silicon surface is then analyzed for the trace level of copper.

Detecting trace levels of copper

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Hamburg, PA, United States of America

Joze E Antol