Lucent Technologies Inc.

Agere Systems Inc.

At+t Corp.

Agere Systems Guardian Corp.

Joze Bevk

Hans-Joachim Ludwig Gossmann

Ran-Hong Yan

Leonard C Feldman

Steven J Hillenius

George E Georgiou

Henry S Luftman

A Passner

Gregory S Boebinger

Matthias Werner Fuertsch

In accordance with the invention, a process for forming a dual gate structure for CMOS devices comprises the steps of a) providing a semiconductor workpiece including n-type and p-type regions and a gate dielectric region for a dual gate structure formed over the regions, b) forming over the gate dielectric region a thin layer of semiconductor doped to one type of conductivity, c) selectively removing the doped semiconductor overlying the workpiece region of like conductivity doping and d) forming a thin layer of semiconductor doped to the opposite kind of conductivity. The doped layers are then planarized as by chemical-mechanical polishing (CMP). An additional layer of undoped semiconductor can optionally be applied to bury the doped layers, and the device can be finished by coating with metal silicide in the usual fashion. This process can be completed with only one photolithography step, simplifying device fabrication by several operations.

Process for the fabrication of dual gate structures for CMOS devices

In accordance with the invention, a silicon gate field effect device is provided with improved control over the distribution of dopants by forming thin buried layer of oxide within the silicon gate. In essence, a silicon gate device is fabricated by the steps of forming a gate dielectric on a silicon substrate and forming a first layer of the silicon gate (amorphous or polycrystalline) on the dielectric. A thin layer of oxide is formed on the first gate layer, and a second silicon gate layer is formed on the oxide, producing a silicon gate containing a thin buried oxide layer. Dopants are then implanted through the second gate layer and the buried oxide, and the device is finished in a conventional manner. The buried oxide layer, acting as a sieve, maintains high dopant concentration near the interface between the gate and minimizes dopant outdiffusion through the gate.

Process for fabricating semiconductor devices in which the distribution of dopants is controlled

A process for device fabrication, comprising the steps of forming a dielectric material region on a silicon substrate, forming a first amorphous silicon or polysilicon region on the dielectric material region, implanting one or more dopants in the first amorphous silicon or polysilicon region, and, subsequent to implanting the one or more dopants in the first amorphous silicon or polysilicon region, forming a second amorphous silicon or polysilicon region on the first amorphous silicon or polysilicon region. Typically, a refractory metal silicide layer is formed over the silicon, and such silicide is optionally formed by a salicide process. The second silicon region makes it more difficult for the implanted dopants to reach the silicide layer, and thereby reduces undesirable lateral diffusion of dopants in the silicide and accompanying cross-doping. The buried nature of the dopants in the silicon further reduces the amount of lateral diffusion within the silicon, regardless of the gate material. In addition, the benefits of a relatively thin gate dielectric are realized. Further, the reduced annealing times and temperatures necessary for dopant drive-in and activation result in improved control of device threshold voltage, on- and off-current, and channel and source/drain dopant profiles.

Process for device fabrication

The invention is directed to a process for forming p.sup.+ and n.sup.+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected to a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is performed after the n-type dopant is implanted into the structure. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n.sup.+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.

Process for fabricating a device using nitrogen implantation into

Methods and apparatus are disclosed for maximizing the strength and deformability of dimensionally-reduced in-situ-formed composites. According the invention, the temperature of the composite is maintained at less than its recrystallization temperature as it is dimensionally reduced, such as by drawing it through one or more dies in a wire-drawing apparatus. The drawing speed and other parameters may be adjusted, as required, to control composite temperature.

Process and apparatus for making in-situ-formed multifilamentary

A process for making a MOS device on a silicon substrate includes the step of forming a buried layer of germanium-silicon alloy in the substrate, or, alternatively, a buried layer of silicon enclosed between thin, germanium-rich layers. This buried layer is doped with boron, and tends to confine the boron during annealing and oxidation steps. The process includes a step of exposing the substrate to an oxidizing atmosphere such that an oxide layer 10 .ANG.-500 .ANG. thick is grown on the substrate.

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Summit, NJ, United States of America

Joze Bevk