Cadence Design Systems, Inc.

Joyjeet Bose

Sachin Shrivastava

Satish Raj

Pardeep Juneja

Jean-Marc Bourguet

Yashu Gupta

Ankur Chaplot

Ying-Hui Wang

The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.

System and method for visualization in an electronic circuit design

Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.

Generating and inserting metal and metal etch shapes in a layout to correct design rule errors

Growing community of inventors

Uttar Pradesh, India

Joyjeet Bose