Intel Corporation

Joydeep Ray

Abhishek R Appu

Altug Koker

Prasoonkumar Surti

Balaji Vembu

Vasanth Ranganathan

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Kamal Sinha

Travis T Schluessler

Ben J Ashbaugh

Linda L Hurd

Kiran Chand Veernapu

Ankur N Shah

Sanjeev S Jahagirdar

Nikos Kaburlasos

Nicolas C Galoppo Von Borries

Murali Ramadoss

Dukhwan Kim

John H Feit

Varghese George

Jacek Kwiatkowski

James A Valerio

Michael S Strickland

Xiaoming Chen

Aravindh V Anantaraman

Ping Tak Tang

John Charles Weast

David M Puffer

Chandrasekaran Sakthivel

Narayan Srinivasa

Anbang Yao

Feng Chen

Wenyin Fu

Pattabhiraman K

Jonathan Kennedy

Sara S Baghsorkhi

Jeffery S Boles

Mike MacPherson

Eriko Nurvitadhi

Mike B Macpherson

Farshad Akhbari

Nadathur Rajagopalan Satish

Lakshminarayanan Striramassarma

Liwei Ma

Tatiana Shpeisman

Karthik Vaidyanathan

Adam T Lake

Stanley J Baran

Devan Burke

Justin E Gottschlich

Rajkishore Barik

Tsung-Han Lin

Narayan Biswal

Josh B Mastronarde

Bhushan M Borole

Guei-Yuan Lueh

Hugues Labbe

Atsuo Kuwahara

Michael Apodaca

Deepak Shashidhar Vembar

Scott R Janus

Sang-Hee Lee

Niranjan L Cooray

Kai Xiao

James M Holland

Abhishek Venkatesh

Gabor Liktor

Gokcen Cilingir

Tomer Bar-On

Richmond Hicks

Peter L Doyle

Changliang Wang

Sanu K Mathew

Kun Tian

Mark A Anders

Himanshu Kaul

Eric C Samson

Ingo Wald

Nausheen Ansari

Aditya Navale

Jill MacDonald Boyce

Rajesh Poornachandran

Rajesh M Sankaran

Zhi Hu Wang

Carsten Benthin

Inder M Sodhi

Ximin Zhang

Christopher E Cox

Selvakumar Panneer

Yi-Jen Chiu

Hong Jiang

Lidong Xu

Blaise B Fanning

Srikanth Kambhatla

Ravishankar Iyer

Shreekant S Thakkar

Jason Daniel Tanner

Zhi Jun Wang

Sridhar Lakshmanamurthy

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.

Sharing register file usage between fused processing resources

Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.

Multicore processor with each core having independent floating point datapath and integer datapath

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

System, apparatus and method for increasing performance in a processor during a voltage ramp

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.

Atomic handling for disaggregated 3D structured SoCs

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

Prefetch status notification for memory prefetching

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Interconnect fabric link width reduction to reduce instantaneous power consumption

Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

Base plus offset addressing for load/store messages

Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

Implicit fence for write messages

Growing community of inventors

Folsom, CA, United States of America

Joydeep Ray